On the Efficacy of Simplified 2D On-chip Inductance Models Tao Lin1 Michael W. Beattie2 Lawrence T. Pileggi Carnegie Mellon University Currently with Monterey Design Currently with IBM

On-Chip Inductance On-chip inductance is becoming a concern in high performance design The use of Copper reduces wiring resistance (R) The increase of signal frequency raises inductive reactance (jL) In recently years, on-chip inductance is becoming one of the concerns for high performance IC designs. This is partially due to the use of copper interconnect which has reduced the unit length wiring resistance. On the other hand, on-chip signals are getting faster. The inductive reactance (jwl) is no longer a negligible part of the total interconnect impedance. As a result, inductance related effects begins to show up in cutting-edge designs.

Modeling On-Chip Inductance Self inductance Mutual inductance Current return paths are not known a priori Partial inductance is the method of choice for 3D on-chip inductance modeling As we know, inductance is a property of current loops. However since the current return paths are unknown, modeling on-chip inductance directly is an classic chicken and egg problem. The key to break the deadlock is “partial inductance” approach. The partial inductance is defined based on a segment and the virtual loops it forms with infinity. The total loop inductance can be computed by combinations of partial inductance.

Complexity Full 3D (three dimensional) inductance analysis is expensive Number of segments is huge Inductance coupling is a long range effect A B C D E F G H capacitance Inductance Although partial inductance models can be very accurate for RLC analysis. The complexity of PEEC RCL analysis greatly surpassed a typical RC analysis. Even for a small design, the number of segments need to be considered could be huge. And inductive couplings is a long range effect. RC analysis often only involves coupling between immediate neighbors, but a full PEEC based RCL model often has to include all the remote couplings. Therefore, unlike the sparse capacitance matrix, inductance matrix is full. ABCDEFGH ABCDEFGH L Zero Non-zero mutual term Self term C

Previous Work Sparse partial inductance matrix methods: Shift-truncate [Krauter95][He97] Equipotential shell [Beattie00] Return limited loop inductance [Shepard00] Virtual Screening [Dammers99] Susceptance [Devgan00][Beattie01] Simplified 2D models Cascaded model [Gala00][Chang00] Normalized model [Xu01] Previously a lot of work has been done to reduce the complexity of inductance analysis. In this paper, we focus on another small class of methods. We call these methods simplified 2D methods since they only include coupling terms into dimensions. They have been shown to be very useful in practice and were presented in publications from several research groups.

2D Inductance Models forward self coupling (3) forward mutual coupling (9) parallel coupling (3+1) Zero Mutual term Self term 3D: Zero Mutual term Self term 2D: Zero Mutual term Self term 3D: Let me explain what are the so called “simplified 2D models”. Suppose we have 4 parallel wires and each of them is divided into 4 segments. Each segment has 3 parallel coupling terms and 1 self terms associated with it. It also has 3 forward coupling terms that are between the up or downstream segments along the same wire. However, they are more. The coupling between the segments which are not exactly aligned are also forward coupling terms. Thus for a discretized multiconductor system like this, the number of

Cascaded Model L L ABCD EFGH ABCDEFGH A B C D E F G H A B C D E F G H One of the commonly seen 2D model is the cascaded model. We simply extract the inductance matrices of each stage of parallel segments separately and than cascade them together to form the matrix for the entire system. In this model the forward coupling terms are not modeled at all, or say, they are truncated and discarded. ABCDEFGH L E F G H

Normalized Model L 1/2x 1/2x L L AE BF CG DH ABCD EFGH ABCDEFGH A B C The normalized approach start with the system of the parallel wires with full length. The total inductance matrix is extracted then scaled to to matrices for each stage. Finally they are put together for the discretized system. Note that although the matrix does not contain forward coupling. Forward coupling effect is included when the matrix for the full length system is generated and then equally distributed into the submatrices as an equivalent parallel coupling effect. ABCDEFGH L

2D Models Advantages: Efficacy: Is forward coupling significant? Greatly improve efficiency in extraction and analysis Guaranteed stability Can be incorporated with other techniques (e.g. windowing, pattern matching) Efficacy: Are they accurate for general interconnect topology? The advantages of simplied 2D models are obvious. It can reduce the memory and runtime complexity by orders of magnitude. It has guaranteed stability. Further more, it make the circuit more regular, so that other techniques such as windowing, pattern matching, table look-up can be very efficiently implemented to further speed up the exdtraction and analysis. But before we can enjoy the advantages, an important issue is that whether this approach can be generally applied to various on-chip interconnect scenarios? To answer this question, we start with another question, how important is the forward coupling effect? Is forward coupling significant?

Inductance Calculation Formulas ([Hoer65], [Grover73]) Mutual inductance between two parallel conductors l d d: arithmetic mean distance (pitch) R: geometric mean distance (GMD) For the simplicity of discussion, we used the expansion formulas of inductance calculation. The longer the segment, the more accurate this formula. Note where R is the geometric mean distance.

Practical Formulas Inductance of wires with rectangular cross sections Self inductance: Mutual inductance: For numerical calculation, we use these two more practical formulas where B and C are the width and thickness. The others are small constant that can be obtained from lookup tables.

Forward Self Coupling Forward coupling partial inductance Mf L

Not negligible! The ratio of the forward coupling term to the self term: If , The ratio asymptotically decrease to zero as segment length increases For practical dimensions, it is not negligible B=C=1um, l=1000um, Mf/L=9.4%

Not Negligible! For wires containing more than two segments Mf1 Mf2 -- Mf/L increases with l2 -- Mf/L is not negligible

Forward Mutual Coupling We have similar conclusions for forward coupling terms between segments of parallel wires If , Mf/Mp decreases to zero logarithmically as length increases For practical wire sizes, forward coupling is not negligible (11.7%) The ratio increases if the wire contains more than 2 segments Mp Mf

Return current Inductance is a property of current loops Current return paths must be taken into account when considering inductance effect

Effective Forward Coupling Forward Coupling between loops A C B d D l1 l2

Effective Forward Coupling B D d l1 l2

Negligible! Forward coupling Inductance between loops approaches constant Loop inductance grows nearly linearly with segment length The effective forward coupling is negligible! True even if the wire contains multi-segments True even if the loops are not exactly aligned.

Current Distribution On-chip interconnect currents return through AC paths formed by coupling capacitors

Two Models CC CC Coplanar structure CC “Cg” “Cg”

Induced Voltage “Cg” j j+1 k k-1 k-2 General case: iint iext

Inductance in Realistic Cases For coplanar structure, forward coupling is negligible. 2D models are accurate (for L>>d). For models with capacitors to ground: If return current via grounding capacitances is significant, discarding forward coupling inductance (as done in the cascaded model) will introduce error. Normalized models capture forward coupling by coupling between parallel terms. ( )

Experiment – Accuracy 3000um long, 5 bit bus with shields Cross section 0.5umx1um, pitch 1um Rd=50ohm, Cload=40ff Input rise time Tr=50ps Consider two circuit models: without grounding capacitance (coplanar structure) with grounding capacitance Fastcap/FastHenry/Hspice Delay vs number of segments

Experiment I Without grounding capacitance, current is forced to return via in-plane return paths Delay (ps) Number of segments

Experiment II Current returning via grounding capacitors Delay(ps) Number of segments

Experiment-III Simulate with faster input signals. Tr=10ps Delay (ps) Number of segments

Experiment -Runtime Compare the Hspice runtime on the full 3D model and the simplified 2D models Runtime (sec) Number of segments

Summary The efficacy of simplified 2D inductance models is studied via calculation of forward coupling inductance 2D models can provide satisfying accuracy as long as the current return can be limited to local return paths Interconnect analysis can be greatly simplified by using 2D inductance models