Model based Design : a firmware perspective …yes, including the CASPER tool-flow. I was asked to take a look @ CASPER tool flow for firmware development. Compelled study the bigger picture i.e. Model based design. Presenting my preliminary understanding of the existing tools and tool flows for Model based design from firmware perspective. Raj Thilak Rajan rajan@astron.nl ASTRON Raj Thilak Rajan Uni-Board FP7 Kickoff meeting Friday, February 27, 2009

Traditional Firmware Development HDL Code Verification Legacy+ IP cores RTL Synthesis FPGA ASIC Manual Coding Specifications Textual specifications Legacy + IP cores -> Shelf code Test benches‘ written, test cases formulated - > Functional verification Manual Coding Time : arguably 40% (or more) of project timeline Translation prone to errors Verification does not quantify the difference between input specifications and final system, for all scenarios. Raj Thilak Rajan Uni-Board FP7 Kickoff meeting Friday, February 27, 2009

Model based Design approach Reference Model ESL Synthesis HDL Code RTL FPGA ASIC Legacy+ IP cores Co-Simulation Reference Model Input specifications + High Level Modeling => Executable Specifications Electronic System Level (ESL) synthesis Automated translation Co-Simulation Verification with Reference Model Raj Thilak Rajan Uni-Board FP7 Kickoff meeting Friday, February 27, 2009

Framework… SIMULINK Reference Model ESL synthesis tool a plug-in Libraries + HDL Generation Only these libraries can be synthesized to HDL ! Raj Thilak Rajan Uni-Board FP7 Kickoff meeting Friday, February 27, 2009

Available tools… Inter-dependence FPGA dependence Co-simulation Simulink + Xilinx System Generator (XSG) Altera DSP Builder (ADG) Synplify DSP (SD) Mathworks HDL Coder (MHC) Model + ESL Synthesis SIMULINK EDA-simulator Co-simulation Xilinx FPGA Only Altera FPGA Only Xilinx and Altera FPGA Inter-dependence Reference Model < > ESL synthesis Tool FPGA dependence 3 Basic Tool Flows : Xilinx , Altera and Generic Co-simulation MathWorks SIMULINK based EDA Co-Simulator for Model-Sim, Discovery and Incisive ESL Synthesis and Co-Simulation Independent Each company caters to its own FPGA Raj Thilak Rajan Uni-Board FP7 Kickoff meeting Friday, February 27, 2009

CASPER – MSSGE MSSGE : Matlab/Simulink/System Generator/ EDK tool-flow Xilinx ONLY MSSGE 10.1 libraries CASPER DSP (50) Communication (2) System Blocks (8) CASPER currently porting MSSGE libraries to Xilinx version 10.1 created by Berkeley Wireless Research Center (BWRC) Raj Thilak Rajan Uni-Board FP7 Kickoff meeting Friday, February 27, 2009

CAPER MSSGE : Pros and Cons  Save time and resources Xilinx (90+) + MSSGE(50) => 140+ reusable blocks available Initial firmware development time reduced Efficiency CASPER -> XSG -> best use of Xilinx FPGA resources  Xilinx dependence Xilinx ONLY blocks Models cannot be ported to other ESL synthesis environments Xilinx Version dependence Stable : Xilinx 7.1 Under Development : Xilinx 10.1 Work arounds costing precious time… Control and Communication board specific blocks (20+) need to be developed Long run : firmware development bound to Xilinx IP? firmware work bench would be obsolete, if we choose alternative. Raj Thilak Rajan Uni-Board FP7 Kickoff meeting Friday, February 27, 2009

Conclusion Model based Design Tools Next Step Next level of abstraction Single click - hardware implementation simplified Caution: Tools not yet standardized for ESL synthesis ! in contrast to VHDL for RTL synthesis Tools Co- simulation : flexible. ESL synthesis : ? ? ? Next Step Investigate alternative generic tool flows Mathworks : HDL Coder Synopsys : Synplicity DSP Need for hybrid tool-flow Model based Design < > Traditional Development Model based Design (use MSSGE libraries) : DSP Manual + Legacy codes : Control and Communication. Raj Thilak Rajan Uni-Board FP7 Kickoff meeting Friday, February 27, 2009