Lab. on Finite State Machine

Slides:

Advertisements

Similar presentations

Introduction to Sequential Circuits

Advertisements

Sequential Circuits Storage elements

State-machine structure (Mealy)

TOPIC : Finite State Machine(FSM) and Flow Tables UNIT 1 : Modeling Module 1.4 : Modeling Sequential circuits.

Computing Machinery Chapter 5: Sequential Circuits.

Digital Logic Design Lecture 27.

Sequential Design Part II. Output A(t+1) =D A = AX + BX B(t+1) =D B = AX Y = AX + BX.

Sequential Circuit Design

1 Homework Reading –Tokheim, Section 5-10, 7-4 Machine Projects –Continue on MP4 Labs –Continue labs with your assigned section.

Review and Overview. Review  Combinational logic circuit – Decoder, Encoder, Multiplexer, De-multiplexer, Full Adder, Multiplier  Sequential logic circuit.

6/12/20151 Sequence Detectors Lecture Notes – Lab 4 Sequence detection is the act of recognizing a predefined series of inputs A sequence detector is a.

CS 140 Lecture 8 Professor CK Cheng 4/26/02. Part II. Sequential Network 1.Memory SR, D, T, JK, 2.Specification S XY s i t+1 = g i (S t, X t )

Sequential Logic Design

Sequential Circuit Design

Overview Sequential Circuit Design Specification Formulation

Chapter 8 -- Analysis and Synthesis of Synchronous Sequential Circuits.

ECE 301 – Digital Electronics Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #17)

ECE 331 – Digital Systems Design Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #19)

Sequential circuit design

ECE/CS 352 Digital System Fundamentals© T. Kaminski & C. Kime 1 ECE/CS 352 Digital Systems Fundamentals Spring 2001 Chapter 4 – Part 3 Tom Kaminski & Charles.

ECE 331 – Digital Systems Design Sequential Logic Circuits: FSM Design (Lecture #20)

Chapter 5 - Part Sequential Circuit Design Design Procedure  Specification  Formulation - Obtain a state diagram or state table  State Assignment.

Analyzing our example circuit

Chap 4. Sequential Circuits

Sequential Circuits. Combinational Circuits + Storage element output depends both on previous state and input Fig. 5-1.

State Machines.

Chapter 8 -- Analysis and Synthesis of Synchronous Sequential Circuits.

Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 5 – Sequential Circuits Part 2 – Sequential.

CPEN Digital System Design Chapter 5 - Sequential Circuits Sequential Circuit Design C. Gerousis © Logic and Computer Design Fundamentals, 4 rd Ed.,

Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 5 – Sequential Circuits Logic and Computer.

9/15/09 - L24 Other FF TypesCopyright Joanne DeGroat, ECE, OSU1 Other FF Types.

Vending Machine Using FSM Aalapee Patel Seth Martin.

ANALYSIS OF SEQUENTIAL CIRCUITS by Dr. Amin Danial Asham.

Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 5 – Sequential Circuits Part 2 – Sequential.

DESIGN OF SEQUENTIAL CIRCUITS by Dr. Amin Danial Asham.

1 State Reduction Goal: reduce the number of states while keeping the external input-output requirements unchanged. State reduction example: a: input 0.

1Sequential circuit design Acknowledgement: Most of the following slides are adapted from Prof. Kale's slides at UIUC, USA by Erol Sahin and Ruken Cakici.

Sequential Design Motivation Sequential processing often more tractable than parallel Example Sequential processing sometimes only method that works Example.

Chapter 8 -- Analysis and Synthesis of Synchronous Sequential Circuits.

Synthesis Synchronous Sequential Circuits synthesis procedure –Word description of problem /hardest; art, not science/ –Derive state diagram & state table.

Sequential Circuit Design Section State Machines Design Procedure 1.Specification- obtain (produce) problem description 2.Formulation - Obtain.

Lecture 22: Finite State Machines with Output. Moore Machine - A Moore machine is a 6-tuple (Q, , , , q 0,  ) where, (1) Q is a finite set of states.

Sequential Circuit: Design BIL- 223 Logic Circuit Design Ege University Department of Computer Engineering.

Common Elements in Sequential Design. Lecture 3 topics  Registers and Register Transfer  Shift Registers  Counters Basic Counter Partial sequence counters.

State Diagrams Tuesday, 12 September State diagram Graphical representation of a state table. –Provides the same information as a state table. –A.

Mealy and Moore Machines Lecture 8 Overview Moore Machines Mealy Machines Sequential Circuits.

Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved.

Overview Part 1 - Storage Elements and Sequential Circuit Analysis

Sequential Circuit Design

ANALYSIS OF SEQUENTIAL CIRCUITS

Adapted by Dr. Adel Ammar

FIGURE 5.1 Block diagram of sequential circuit

Sequential Circuit: Counter

Digital Design Lecture 9

ECE 301 – Digital Electronics

FINITE STATE MACHINES (FSMs)

KU College of Engineering Elec 204: Digital Systems Design

Sequential circuit design

Sequential circuit design

CSE 370 – Winter Sequential Logic-2 - 1

Sequential circuit design

KU College of Engineering Elec 204: Digital Systems Design

EE2174: Digital Logic and Lab

MTE 202, Summer 2016 Digital Circuits Dr.-Ing. Saleh Hussin

Instructor: Alexander Stoytchev

SYEN 3330 Digital Systems Chapter 6 – Part 3 SYEN 3330 Digital Systems.

Chapter5: Synchronous Sequential Logic – Part 4

Sequential Circuit Analysis

Chapter5: Synchronous Sequential Logic – Part 3

Presentation transcript:

Lab. on Finite State Machine Sequence Recognizer

Homework #3 Output Z=1 when 1101 is recognized Design a circuit to recognize the sequence 1101 in a input sequence Output Z=1 when 1101 is recognized Thus, the sequential machine must remember that the first two one's have occurred as it receives another symbol. Also, the sequence 1101101 contains 1101 as both an initial subsequence and a final subsequence with some overlap, i. e., 1101101 or 1101101. The sequence 1101 must be recognized each time it occurs in the input sequence.

State Diagram (Moore model) B/0 C/0 D/0 E/1 1 Use: JK F.F. binary coding for the states “don’t care” for unused states

Simulation Feed a sequence containing 1101 into the designed circuit Show the output and states of the circuit