Computer Organization And Assembly Language II Prof. Muhammad Saeed

Computer Architecture & Assembly Language X86 Processor Assembly Language 1/27/2015 Computer Architecture & Assembly Language

Computer Architecture & Assembly Language Fundamentals (recap) Number System Binary Octal Hexa Conversion into one another Binary Operations Addition, Subtraction and Multiplication AND, OR, XOR COMPLEMENT, TWO’s COMPLEMENT Set and Reset Bits 1/27/2015 Computer Architecture & Assembly Language

Computer Architecture & Assembly Language Interrupts An interrupt is a signal to the processor emitted by hardware or software indicating an event that needs immediate attention. An interrupt alerts the processor to a high-priority condition requiring the interruption of the current code the processor is executing. The processor responds by suspending its current activities, saving its state, and executing a function called an interrupt handler (or an interrupt service routine, ISR) to deal with the event. This interruption is temporary, and, after the interrupt handler finishes, the processor resumes normal activities.  1/27/2015 Computer Architecture & Assembly Language

Computer Architecture & Assembly Language Interrupt 1/27/2015 Computer Architecture & Assembly Language

Computer Architecture & Assembly Language Interrupts TYPES Hardware interrupts are used by internal or external devices to communicate that they require attention from the operating system. Pressing a key on the keyboard or moving the mouse triggers hardware interrupts that cause the processor to read the keystroke or mouse position. Unlike the software type hardware interrupts are asynchronous and can occur in the middle of instruction execution. A software interrupt is caused either by an exceptional condition in the processor itself, or a special instruction in the instruction set which causes an interrupt when it is executed. The former is often called a trap or exception and is used for errors or events occurring during program. For example, if the processor's arithmetic logic unit is commanded to divide a number by zero, this impossible demand will cause a divide-by-zero exception. Computers often use software interrupt instructions to communicate with the device drivers. 1/27/2015 Computer Architecture & Assembly Language

Computer Architecture & Assembly Language Interrupts Interrupt Service Routine (ISR) or Interrupt handler: Code used for handling a specific interrupt. Interrupt priority: In systems with more than one interrupt inputs, some interrupts have a higher priority than other. They are serviced first if multiple interrupts are triggered simultaneously. Interrupt vector: Code loaded on the bus by the interrupting device that contains the Address (segment and offset) of specific interrupt service routine. Interrupt Masking: Ignoring (disabling) an interrupt Non-Maskable Interrupt (NMI): Interrupt that cannot be ignored (power-down) 1/27/2015 Computer Architecture & Assembly Language

Computer Architecture & Assembly Language The Intel x86 Vector Interrupts 8088/8086 processor as well as 80386/80486/ Pentium etc. processors operating in Real Mode (16-bit operation) The processor uses the interrupt vector to determine the address of the ISR of the interrupting device. The interrupt vector is a pointer to the Interrupt Vector Table. The Interrupt Vector Table occupies the address range from 00000H to 003FFH (the first 1024 bytes in the memory map). Each entry in the Interrupt Vector Table is 4 bytes long: The first two represent the offset address and the last two the segment address of the ISR. The first 5 vectors are reserved by Intel to be used by the processor. The vectors 5 to 255 are free to be used by the user. 1/27/2015 Computer Architecture & Assembly Language

Computer Architecture & Assembly Language The Intel x86 Vector Interrupts ••••• Type-0 Type-1 Type-255 IP CS 003FFH Interrupt Vector Table 8088/8086 processor as well as 80386/80486/ Pentium etc. processors operating in Real Mode (16-bit operation) 1/27/2015 Computer Architecture & Assembly Language

Computer Architecture & Assembly Language Interrupt Vector Table – Real Mode Using the Interrupt Vector Table shown below, determine the address of the ISR of a device with interrupt vector 42H. Answer: Address in table = 4 X 42H = 108H Offset Low = [108] = 2A, Offset High = [109] = 33 Segment Low = [10A] = 3C, Segment High = [10B] = 4A Address = 4A3C:332A = 4A3C0 + 332A = 4D6EAH 1/27/2015 Computer Architecture & Assembly Language

Computer Architecture & Assembly Language The Intel x86 Vector Interrupts 80386/80486/Pentium processors operating in Protected Mode (32-bit operation) The interrupt vector is a pointer to the Interrupt Descriptor Table. The Interrupt Descriptor Table can be located anywhere in the memory. Its starting address is pointed by the Interrupt Descriptor Table Register (IDTR). Each entry in the Interrupt Vector Table is 8 bytes long: Four bytes represent the 32-bit offset address, two the segment selector and the rest information such as the privilege level. The first 32 vectors are reserved by Intel to be used by the processor. The vectors 33 to 255 are free to be used by the user. 1/27/2015 Computer Architecture & Assembly Language

Computer Architecture & Assembly Language The Intel x86 Vector Interrupts 1/27/2015 Computer Architecture & Assembly Language

Computer Architecture & Assembly Language Fundamentals Little-Endians x86 processors store and retrieve data from memory using little-endian order(low to high). The least significant byte is stored at the first memory address allocated for the data. The remaining bytes are stored in the next consecutive memory positions. The doubleword 12345678h is stored as given in the opposite figure. Big-Endians Some other computer systems use big-endian order (high to low). Figure on the right shows the same example of 12345678h stored in big-endian order 1/27/2015 Computer Architecture & Assembly Language

Computer Architecture & Assembly Language Language Fundamentals Identifiers An identifier is a programmer-chosen name. It might identify a variable, a constant, a procedure, or a code label. There are a few rules on how they can be formed: • They may contain between 1 and 247 characters. • They are not case sensitive. • The first character must be a letter (A..Z, a..z), underscore (_), @ , ?, or $. Subsequent characters may also be digits. • An identifier cannot be the same as an assembler reserved word. 1/27/2015 Computer Architecture & Assembly Language

Computer Architecture & Assembly Language Language Fundamentals Data Types 1/27/2015 Computer Architecture & Assembly Language

Computer Architecture & Assembly Language Language Fundamentals 8088 Data Type Directives 1/27/2015 Computer Architecture & Assembly Language

Computer Architecture & Assembly Language Language Fundamentals Label A label is an identifier that acts as a place marker for instructions and data. A label placed just before an instruction implies the instruction’s address. Similarly, a label placed just before a variable implies the variable’s address. There are two types of labels: Data labels and Code labels. A data label identifies the location of a variable, providing a convenient way to reference the variable in code. Data Label: a1 BYTE 86 ( a1 is Data Label) Code Label: again: mov eax, 100h (again is Code Label) 1/27/2015 Computer Architecture & Assembly Language

Computer Architecture & Assembly Language Language Fundamentals Directive And Instruction Directive instructs assembler how to assemble a program, in other word it is an instruction for the assembler whereas assembly Instruction is for the processor and it is converted to machine code. Directive is not converted to machine code. Directives do not execute at runtime, but they let you define variables, macros, and procedures. They can assign names to memory segments and perform many other housekeeping tasks related to the assembler. Directives: INCLUDE (INCLUDE windows.inc, INCLUDELIB windows.lib), .MODEL,.DATA, .CODE, WORD, etc. 1/27/2015 Computer Architecture & Assembly Language

Computer Architecture & Assembly Language Language Fundamentals Defining Data a1 BYTE 86 a2 BYTE ‘K’ a3 BYTE “Welcome to Dept. of Comp. Sc. & IT”,0 a4 BYTE 255 a5 BYTE ? a6 SBYTE -128 a7 SBYTE 127 a8 SBYTE 0, 20, 50, -25, 100 quote BYTE “There are no tales” BYTE “ finer than those”, 0dh, 0ah BYTE “created by life itself”,0dh, oah,0 1/27/2015 Computer Architecture & Assembly Language

Computer Architecture & Assembly Language Language Fundamentals Defining Data (ARRAYS) Array1 BYTE 10 DUP(?) Array2 WORD 20 DUP(0) Array3 BYTE 10 DUP(‘COMPUTER’) Stack (.stack 1024) Data (.data) Code (.code) Segments Comments single line comment starts with “;” and the block comment is used as, COMMENT ! …….. ………………….. ! (! Character can be replaced by & etc.) 1/27/2015 Computer Architecture & Assembly Language

Language Fundamentals Stack Stack is a memory array managed directly by the CPU, using the ESP register, known as the stack pointer register. In 32-bit mode, ESP register holds a 32-bit offset into some location on the stack. We rarely manipulate ESP directly; instead, it is indirectly modified by instructions such as CALL, RET, PUSH, and POP. Stack, before and after pushing 00000001 and 00000002 Before After

Computer Architecture & Assembly Language Memory Addressing 1/27/2015 Computer Architecture & Assembly Language

Language Fundamentals Data-Related Operators and Directives The OFFSET operator returns the distance of a variable from the beginning of its enclosing segment. The PTR operator lets you override an operand’s default size. The TYPE operator returns the size (in bytes) of an operand or of each element in an array. The LENGTHOF operator returns the number of elements in an array. The SIZEOF operator returns the number of bytes used by an array initializer. The LABEL directive provides a way to redefine the same variable with different size attributes.

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