EDMG Header-B Encoding and Modulation for SC PHY in 11ay

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Presentation transcript:

EDMG Header-B Encoding and Modulation for SC PHY in 11ay July 2016 doc.: IEEE 802.11-16/XXXXr0 July 2016 EDMG Header-B Encoding and Modulation for SC PHY in 11ay Date: 2016-07-25 Authors: Intel Corporation Intel Corporation

July 2016 Introduction This presentation defines the EDMG Header-B encoding and modulation for SC PHY MU-MIMO transmission, [1]. The proposed method is based on the encoding and modulation defined for the legacy SC PHY in 11ad standard, [2]. Intel Corporation

EDMG Header-B Format Proposed Header-B bit content: July 2016 The exact bit content of Header-B is not defined yet; It is proposed: First 7 bits (b1, b2, …, b7) – define scrambler seed per user (or STA); The total header size it is proposed to limit by 64 bits; The rest of bits may define the PSDU length in bytes per user; EDMG-MCS per user; Other parameters; Intel Corporation

EDMG Header-B Encoding July 2016 EDMG Header-B Encoding EDMG Header-B encoding steps, [2]: Data scrambling: b = (b1, b2, …, b64) – input bits of Header-B; s = (01, 02, 07, s1, s2, …, s57) – s1, s2, …, s57 are first 57 bits at the output of scrambler with initial seed value (b1, b2, …, b7); bs = b × s; × - defines bitwise XOR of two vectors; Data encoding: c = (bs1, bs2, …, bs64, 01, 02, …, 0440, p1, p2, …, p168) – LDPC codeword; HcT = 0 – encoding, H is a 168 x 672 LDPC ¾ parity check matrix; c1 = (bs1, bs2, …, bs64, p1, p2, …, p160) – codeword #1, shortening of zero bits, puncturing of tail parity bits; c2 = (bs1, bs2, …, bs64, p1, p2, …, p152, p161, p162, …, p168) – codeword #2, shortening of zero bits, puncturing of middle parity bits; Intel Corporation

EDMG Header-B Encoding (Cont’d) July 2016 EDMG Header-B Encoding (Cont’d) EDMG Header-B encoding steps (cont’d): Resulting codeword: c = (c1, c2) – codeword of length 448 bits; Codeword scrambling: s = (01, 02, …, 0224, s1, s2, …, s224) - s1, s2, …, s224 are first 224 bits at the output of scrambler with initial seed value (11, 12, …, 17); cs = c × s - bitwise XOR of two vectors; Intel Corporation

Header-B MU-MIMO Transmission July 2016 Header-B MU-MIMO Transmission Access Point (AP) transmits one stream per user: NSTS – total number of space-time streams; “i” – space-time stream index, i=1:NSTS; During MU-MIMO transmission each user (or STA) has its own scrambler initial seed value bi = (b1, b2, …, b7)i depending on the space-time stream index “i”; If each user has single stream, then the initial seed selection guarantees that each user will have its own unique code vector csi; Intel Corporation

Header-B MU-MIMO Transmission (Cont’d) July 2016 Header-B MU-MIMO Transmission (Cont’d) If AP transmits N streams per user: AP creates more than one codeword per user transmitted in different space-time streams; N codewords for N streams are obtained by the bitwise XOR operation applied to the original codeword: cs1 = c × s1, cs2 = c × s2, … csN = c × sN; c – original code vector introduced above; s1 = (01, 02, …, 0224, s1, s2, …, s224) – scrambler vector for stream #1; s2 = (s225, s226, …, s672) – scrambler vector for stream #2; … sN = (s(N-1)*448-224+1, s(N-1)*448-224+2, …, sN*448-224) – scrambler vector for stream #N; All bits: s1, s2, …, sN*448-224 are obtained from the output of scrambler with initial seed (11, 12, …, 17); Intel Corporation

Header-B Modulation & Symbol Blocking July 2016 Header-B Modulation & Symbol Blocking Header-B modulation: Each codeword csi for space-time stream with index “i” is modulated using π/2-BPSK modulation; It provides a SC symbol block blki of length 448 chips for the i-th stream; Each block blki is prepended with Guard Interval (GI) which is a Golay Gai64 sequence of length 64 chips; {Gai64, i=1:NSTS} – comprises the set of mutually orthogonal Ga Golay sequences; This provides a regular SC symbol blocking for the i-th space-time stream as follows: [Gai64, blki]; Intel Corporation

Symbol Blocking for Channel Bonding July 2016 Symbol Blocking for Channel Bonding Symbol blocking in case of channel bonding: NCB = 2, 3, 4 – channel bonding factor; NGI CB = 64 * NCB = 128, 192, 256 – Guard Interval (GI) length in case of channel bonding; The symbol block blki is repeated NCB number of times to support different channel bonding factors: NCB = 2: [Gai128, blki, blki]; NCB = 3: [Gai192, blki, blki, blki]; NCB = 4: [Gai256, blki, blki, blki, blki]; Intel Corporation

July 2016 Conclusions This presentation defines the EDMG Header-B encoding and modulation for SC PHY. Intel Corporation

Straw Poll #1 Would you agree to insert the following in the SFD:” July 2016 Straw Poll #1 Would you agree to insert the following in the SFD:” The 11ay specification shall define first 7 bits of EDMG-Header-B for scrambler seed value and define the total number of bits to 64 as in the legacy 11ad header. “ Intel Corporation

Straw Poll #2 Would you agree to insert the following in the SFD:” July 2016 Straw Poll #2 Would you agree to insert the following in the SFD:” The 11ay specification shall define encoding and modulation method for EDMG-Header-B as described in the 11-16-0989-00-00ay. “ Intel Corporation

References 11-15-1358-04-00ay-specification-framework-for-tgay July 2016 References 11-15-1358-04-00ay-specification-framework-for-tgay Draft P802.11REVmc_D5.4 Intel Corporation