Programming Microcontroller ADC – Analog Digital Converter 3- 1 Programming Microcontroller ADC – Analog Digital Converter Week 3 – Spring Term 2017 32K Byte Burst Flash 64K or 96K Byte SRAM 256K or 512K Byte Burst Flash OTP Mem UART I2C SPI TIM RTC EXT. Bus GPIO USB 2.0FS CAN 2.0B Enet MAC PFQ BC DMA INTR Cntl ARM966E CORE w/DSP 96 MHz CLK Cntl ADC LVD BOD PLL JTAG ETM9 STM32F407

ADC Specifics 12-bit, 10-bit, 8-bit or 6-bit configurable resolution 3- 2 12-bit, 10-bit, 8-bit or 6-bit configurable resolution Interrupt generation Single and continuous conversion modes Scan mode for automatic conversion of channel 0 to channel ‘n’ Data alignment with in-built data coherency Channel-wise programmable sampling time External trigger option with configurable polarity for both regular and injected conversions Discontinuous mode Dual/Triple mode (on devices with 2 ADCs or more) Configurable DMA data storage in Dual/Triple ADC mode Configurable delay between conversions in Dual/Triple interleaved mode ADC conversion type (refer to the datasheets) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at slower speed ADC input range: VREF– ≤ VIN ≤ VREF+ DMA request generation during regular channel conversion

ADC Block diagram (page 389/1745) 3- 3

ARM Peripheral Bus 2 access (APB2) ADC ARM Peripheral Bus 2 access (APB2) 2- 4 Reference Page 72/185 of “STM32F405xx STM32F407xx” “Datasheet – production data”

STM32F40x pin and ball definitions ADC 2- 5 Reference: page 45/185 of “STM32F405xx STM32F407xx” “Datasheet – production data”

ADC register map (431/1745 of RM0090) 3- 6

ADC Status Register (ADC_SR) (416/1745 of RM0090) 3- 7 Address Offset : 0 EOC : Regular channel end of conversion 0 : Conversion not complete 1 : Conversion complete

ADC Control Register 1 (ADC_CR1) (416/1745 of RM0090) 3- 8 Address offset : 0x04 RES : Resolution 00 : 12-bit (15 ADCCLK cycles) 01 : 01: 10-bit (13 ADCCLK cycles) 10 : 10: 8-bit (11 ADCCLK cycles) 11 : 6-bit (9 ADCCLK cycles)

ADC Control Register 2 (ADC_CR2) (418/1745 of RM0090) 3- 9 Address offset : 0x08 ADON : A/D Converter ON / OFF 0 : Disable ADC conversion and go to power down mod 1 : Enable ADC SWSTART : Start conversion of regular channels 0: Reset state 1: Starts conversion of regular channels

ADC sample time register 1 & 2 (420/1745 of RM0090) 3- 10 Address offset : 0x0C & 0x10 SMPx[2:0] : Channel x sampling time selection 000: 3 cycles 001: 15 cycles 010: 28 cycles 011: 56 cycles 100: 84 cycles 101: 112 cycles 110: 144 cycles 111: 480 cycles

ADC regular sequence registers 1, 2 & 3 (423/1745 of RM0090) 3- 11 Address offset : 0x2C, 0x30 & 0x34 L[3:0] : Regular channel sequence length 0000: 1 conversion 0001: 2 conversions ... 1111: 16 conversions SQx[4:0] : 16th conversion in regular sequence Channel number (0..18) assigned as the xth conversion sequence

ADC Regular Data Register (ADC_DR) (425/1745 of RM0090) 3- 12 Address offset: 0x4C DATA[15:0] : Regular data

ADC Initialization of pin PB0 3- 13 GPIOB Module GPIO Mode Register (GPIOx_MODER) Choose analog mode for the pin 0 (MODER0[1:0] = 0b11) GPIO port pull-up/pull-down register (GPIOx_PUPDR) Choose pull-up for the pin 0 (PUPDR0[1:0] = 0b01) ADC1 Module ADC Control Register 1 (ADC_CR1) Set the conversion resolution to 10 bits (RES[1:0] = 0b01) ADC Control Register 2 (ADC_ACR2) Switch the converter on (ADON = 0b1) ADC Sample Time Registers (ADC_SMPR1 & ADC_SMPR2) Set the sampling time for the channel 8 to 15 cycles (SMP8[2:0] = 0b001) ADC Regular Sequence Registers (ADC_SQR1 … ADC_SQR3) Choose the channel 8 for the first sequence (SQ1[4:0] = 0b01000)

Start an ADC Conversion on PB0 3- 14 ADC1 Module ADC Control Register 2 (ADC_ACR2) Start a conversion with the SWSTART bit ADC Status Register (ADC_SR) Wait until the conversion has been realized (EOC bit) ADC Regular Data Register(ADC_DR) Read the conversion result