LOW-POWER COMPARATOR DESIGN BASED ON CMOS DYNAMIC LOGIC CIRCUIT Paper Presentation of Chandrahash Patel Guided by : Dr. Veena C.S. Technocrats of Institute of Technology Rajiv Gandhi Technical University Bhopal

Overview Introduction CMOS Dynamic Logic Design Implementation Simulation Result & Discussion Conclusion and Future research References

Introduction In today’s scenario technology is very important in terms of power consumption. Previously Static CMOS circuits were used which found to be slow as each signal has to drive both NMOS & PMOS transistor so to overcome that Dynamic logic was introduced which works or operates only NMOS transistors which in turn increases the speed and hence improves the overall performance of circuit. Many researchers are working in this field just to improve the performance so that its applications just not only includes microprocessor but DSP (Digital Signal Processing) and Memory too.

CMOS DYNAMIC LOGIC Dynamic logic (sometimes called clocked logic) is temporary (transient) since output levels will remain valid only for a certain period of time. It was popular in 1970s and has seen a recent resurgence in the design of high speed digital electronics, particularly computer CPUs This logic is normally done with charging and selectively discharging capacitance (i.e. capacitive circuit nodes) Precharge clock to charge the capacitance Evaluate clock to discharge the capacitance depending on condition of logic inputs

Conventional CMOS Dynamic Logic Diagram & example Out Clk A B C Mp Me Out Clk A B C Mp Me off Clk Mp on 1 CL ((AB)+C) In1 In2 PDN In3 Clk Me off on Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1)

Another way of representing CMOS Dynamic Logic

Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state stored.

Merits: Avoids duplicating logic twice as in standard CMOS Typically can be used in very high performance applications Very simple sequential memory circuits High density achievable Consumes less power Demerits: Clock synchronization and timing problem Difficult to design

Design Implementation & Simulation Here in this paper Half Precharged CMOS dynamic logic (HPCD) is used which means it is charged to Vdd/2 during Precharge phase and then pulled to Vdd or down to ground during evaluation phase. And then based on HPCD a comparator is used as shown in figure so that optimization of power can be done. For design implementation DSCH and then For simulation Microwind tool is used as shown in flowchart.

Design of HPCD is based on conventional CMOS dynamic logic with difference that source voltage here is Vdd/2 and then comparator added for comparing the reference and DNC voltage Working : Precharge phase: Mp charges DNC to Vdd/2 Evaluation phase: Mk is turned on to charge DNC to VDD as output of comparator is low and if PDN pulls down DNC Mk is turned off and gets it to ground

HPCD based comparator

In above structure some problem were found as Current leakage during precharge phase As in evaluation phase when charged to VDD a DC path is developed which is for whole phase and for next phase too and due to his DC path DC power dissipation appears at M2 & M4 So to reduce that a new comparator design is proposed which overcomes such problems shown in next figure where M1 & M2 :- pre charge, M3-M6 :- two cross coupled inverter forming latch M7 & M8 :- as input transistors and M9

Proposed Comparator Here in this proposed comparator considering Precharge phase when CLK is low M9 is off ,M1 and M2 are turned ON and charges out shown in figure to V and with respect to it M5, M6 are ON. And in Evaluation phase when clock is high M1 & M2 are off, M9 is ON while M7 & M8 works as two variable resistors.

As in precharge phase when DNC (shown in figure as output ) charges to Vdd/2 Mg is off and Mp2 is on which makes input node of output inverter high as it is charged so it reduces DC power dissipation. And in evaluation phase as output of inverter in form of voltage is high which forces Mk to turn off and as result no DC path appears between Vdd/2 to Vdd

Layout and Analog Simulation of HPCD and Proposed Comparator

Power Dissipation (mW) RESULT TABLE Parameters HPCD based Comparator PROPOSED Comparator Power supply (V) 1 Technology used (nm) 70 Estimated Area (µm2) 48.0 130.9 Power Dissipation (mW) 0.357 0.01653 Delay (ps) 53 36 Power Delay Product ( mW *ps) 18.9422 0.59508

Graphical Analysis of Result

CONCLUSION In this paper it is found that the problems which is found in HPCD based comparator is being improved in proposed comparator. Here power dissipation decreases by 95.2% and power delay product (PDP) by 96.8%. So this structure can be used for improving other performance too and even used in DSP, microprocessor etc.

References Song Jha, Shigong Lyn, Qinglong Meng, Fengfeng Wu, Heqing Xu “A new Low-power CMOS Dynamic Logic circuit” 978-1-4673-2523-3/13 IEEE in 2013. M. R. Prasad, D. Kirkpatrick, and R. K. Brayton, “Domino Logic Synthesis and Technology Mapping”, in International Workshop on Logic Synthesis, 1987. P. M. Figueiredo and J. C. Vital, “Kickback noise reduction technique for CMOS latched comapartors,” IEEE Trans. Circuits Syst. II, Exp.Briefs, vol. 53, no. 7, pp. 541–545, Jul. 2006. L.Ding and P. MAzumdar,” On circuit techniques to improve Noise immunity of CMOS dynamic Logic”, IEE transaction on Circuits and System, vol 12,pp. 910-925, September 2004.

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