VLSI Physical Design Automation

Slides:



Advertisements
Similar presentations
Group: Wilber L. Duran Duo (Steve) Liu
Advertisements

Multilevel Hypergraph Partitioning Daniel Salce Matthew Zobel.
L30: Partitioning 성균관대학교 조 준 동 교수
A Graph-Partitioning-Based Approach for Multi-Layer Constrained Via Minimization Yih-Chih Chou and Youn-Long Lin Department of Computer Science, Tsing.
1 Advancing Supercomputer Performance Through Interconnection Topology Synthesis Yi Zhu, Michael Taylor, Scott B. Baden and Chung-Kuan Cheng Department.
Meng-Kai Hsu, Sheng Chou, Tzu-Hen Lin, and Yao-Wen Chang Electronics Engineering, National Taiwan University Routability Driven Analytical Placement for.
1 Physical Hierarchy Generation with Routing Congestion Control Chin-Chih Chang *, Jason Cong *, Zhigang (David) Pan +, and Xin Yuan * * UCLA Computer.
Coupling-Aware Length-Ratio- Matching Routing for Capacitor Arrays in Analog Integrated Circuits Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang and Hui-Fang.
Rajat K. Pal. Chapter 3 Emran Chowdhury # P Presented by.
Introduction to Approximation Algorithms Lecture 12: Mar 1.
MCFRoute: A Detailed Router Based on Multi- Commodity Flow Method Xiaotao Jia, Yici Cai, Qiang Zhou, Gang Chen, Zhuoyuan Li, Zuowei Li.
ICS 252 Introduction to Computer Design Routing Fall 2007 Eli Bozorgzadeh Computer Science Department-UCI.
38 th Design Automation Conference, Las Vegas, June 19, 2001 Creating and Exploiting Flexibility in Steiner Trees Elaheh Bozorgzadeh, Ryan Kastner, Majid.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 21: April 15, 2009 Routing 1.
VLSI Routing. Routing Problem  Given a placement, and a fixed number of metal layers, find a valid pattern of horizontal and vertical wires that connect.
A General Framework for Track Assignment in Multilayer Channel Routing (Multi layer routing) -VLSI Layout Algorithm KAZY NOOR –E- ALAM SIDDIQUEE
Routing 1 Outline –What is Routing? –Why Routing? –Routing Algorithms Overview –Global Routing –Detail Routing –Shortest Path Algorithms Goal –Understand.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 19: April 9, 2008 Routing 1.
Multi-Layer Channel Routing Complexity and Algorithm Rajat K. Pal.
Metal Layer Planning for Silicon Interposers with Consideration of Routability and Manufacturing Cost W. Liu, T. Chien and T. Wang Department of CS, NTHU,
VLSI Physical Design Automation Prof. David Pan Office: ACES Lecture 18. Global Routing (II)
Multi-Layer Channel Routing Complexity and Algorithm Rajat K. Pal.
Chapter 5: Computational Complexity of Area Minimization in Multi-Layer Channel Routing and an Efficient Algorithm Presented by Md. Raqibul Hasan Std No.
7/13/ EE4271 VLSI Design VLSI Routing. 2 7/13/2015 Routing Problem Routing to reduce the area.
General Routing Overview and Channel Routing
Chih-Hung Lin, Kai-Cheng Wei VLSI CAD 2008
Introduction to Routing. The Routing Problem Apply after placement Input: –Netlist –Timing budget for, typically, critical nets –Locations of blocks and.
Domain decomposition in parallel computing Ashok Srinivasan Florida State University COT 5410 – Spring 2004.
MGR: Multi-Level Global Router Yue Xu and Chris Chu Department of Electrical and Computer Engineering Iowa State University ICCAD
A Topology-based ECO Routing Methodology for Mask Cost Minimization Po-Hsun Wu, Shang-Ya Bai, and Tsung-Yi Ho Department of Computer Science and Information.
9/4/ VLSI Physical Design Automation Prof. David Pan Office: ACES Detailed Routing (I)
Authors: Jia-Wei Fang,Chin-Hsiung Hsu,and Yao-Wen Chang DAC 2007 speaker: sheng yi An Integer Linear Programming Based Routing Algorithm for Flip-Chip.
Escape Routing For Dense Pin Clusters In Integrated Circuits Mustafa Ozdal, Design Automation Conference, 2007 Mustafa Ozdal, IEEE Trans. on CAD, 2009.
Global Routing.
1 Coupling Aware Timing Optimization and Antenna Avoidance in Layer Assignment Di Wu, Jiang Hu and Rabi Mahapatra Texas A&M University.
10/7/ VLSI Physical Design Automation Prof. David Pan Office: ACES Lecture 6. Floorplanning (1)
TSV-Aware Analytical Placement for 3D IC Designs Meng-Kai Hsu, Yao-Wen Chang, and Valerity Balabanov GIEE and EE department of NTU DAC 2011.
Solving Hard Instances of FPGA Routing with a Congestion-Optimal Restrained-Norm Path Search Space Keith So School of Computer Science and Engineering.
Archer: A History-Driven Global Routing Algorithm Mustafa Ozdal Intel Corporation Martin D. F. Wong Univ. of Illinois at Urbana-Champaign Mustafa Ozdal.
An Efficient Clustering Algorithm For Low Power Clock Tree Synthesis Rupesh S. Shelar Enterprise Microprocessor Group Intel Corporation, Hillsboro, OR.
1 CS612 Algorithms for Electronic Design Automation CS 612 – Lecture 8 Lecture 8 Network Flow Based Modeling Mustafa Ozdal Computer Engineering Department,
Maze Routing مرتضي صاحب الزماني.
Massachusetts Institute of Technology 1 L14 – Physical Design Spring 2007 Ajay Joshi.
Register Placement for High- Performance Circuits M. Chiang, T. Okamoto and T. Yoshimura Waseda University, Japan DATE 2009.
1 Efficient Obstacle-Avoiding Rectilinear Steiner Tree Construction Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang National Taiwan.
6/5/ VLSI Physical Design Automation Prof. David Pan Office: ACES Detailed Routing (III)
ECE 260B – CSE 241A /UCB EECS Kahng/Keutzer/Newton Physical Design Flow Read Netlist Initial Placement Placement Improvement Cost Estimation Routing.
CALTECH CS137 Winter DeHon CS137: Electronic Design Automation Day 13: February 20, 2002 Routing 1.
Detailed Routing مرتضي صاحب الزماني.
Maze Routing Algorithms with Exact Matching Constraints for Analog and Mixed Signal Designs M. M. Ozdal and R. F. Hentschke Intel Corporation ICCAD 2012.
1 L25 : Crosstalk-Concerned Physical Design (2) Jun Dong Cho Sungkyunkwan Univ. Dept. ECE Homepage :
1 CS612 Algorithms for Electronic Design Automation CS 612 – Lecture 8 Lecture 8 Network Flow Based Modeling Mustafa Ozdal Computer Engineering Department,
High-Performance Global Routing with Fast Overflow Reduction Huang-Yu Chen, Chin-Hsiung Hsu, and Yao-Wen Chang National Taiwan University Taiwan.
2/27/ VLSI Physical Design Automation Prof. David Pan Office: ACES Detailed Routing (II)
An Exact Algorithm for Difficult Detailed Routing Problems Kolja Sulimma Wolfgang Kunz J. W.-Goethe Universität Frankfurt.
EE4271 VLSI Design VLSI Channel Routing.
CALTECH CS137 Fall DeHon 1 CS137: Electronic Design Automation Day 21: November 28, 2005 Routing 1.
Placement and Routing Algorithms. 2 FPGA Placement & Routing.
VLSI Physical Design Automation
VLSI Physical Design Automation
VLSI Physical Design Automation
Design and Analysis of Algorithm
Multilevel Full-Chip Routing for the X-Based Architecture
ESE535: Electronic Design Automation
Iterative Deletion Routing Algorithm
EE4271 VLSI Design, Fall 2016 VLSI Channel Routing.
VLSI Physical Design Automation
A Few Sample Reductions
ICS 252 Introduction to Computer Design
Under a Concurrent and Hierarchical Scheme
Presentation transcript:

VLSI Physical Design Automation Detailed Routing (III) Prof. David Pan dpan@ece.utexas.edu Office: ACES 5.434

Channel/Switch Box Routing Algorithm Graph theory based algorithm Yoshimura and Kuh Greedy algorithm Rivest and Fiduccia Maze routing and its variations Lee, Robin, Soukup, Ohtsuki Hierarchical wire routing Burstein and Pelavin Channel routing Channel / switchbox and general area routing

Over-the-Cell Routing Channel width can be reduced if some nets can be routed outside the channel. The metal layers available over the cell rows can be used for routing. (It is possible due to the limited use of the M2 metal layer within the cells.) Commonly used in standard-cell design.

Two-Layer Over-the-Cell Router “Over-the-Cell Channel Routing”, J. Cong and C. L. Liu, TCAD, pages 408-418, 1990.

Boundary Terminal Model (BTM) Terminal Rows VDD GND

The Routing Problem Boundary Terminal Model (BTM) Two routing layers in the channel. One routing layer for over-the-cell routing, so the routing must be planar. 1 2 1 5 2 5 4 3 4 3 5 2 1 4 1 5 3 6 5 6 3 3

Hyper-terminal A Hyper-terminal is a set of terminals connected by over-the-cell wires. Hyper-terminals: {A,C}, {B}, {D,F,K}, {E}, {G,I}, {H}, {J} A B C D E F G H I J K 1 2 1 5 2 5 4 3 4 3 5 2 1 4 1 5 3 6 5 6 3 3 L M N O P Q R S T U V Hyper-terminals: {L}, {M,O}, {N}, {P}, {Q,U,V}, {R,T}, {S}

Three Steps of the Algorithm Routing over the cells. Select a net segment from each multi-terminal net to be connected in the channel. Routing in the channel.

Routing Over the Cells Reduced to a Multi-Terminal Single-Layer One-Sided Routing Problem (MSOP). Solved by dynamic programming.

MSOP The fewer the number of hyper-terminals resulted, the simpler the subsequent channel routing problem. Routing a row of terminals using a single routing layer on one side of the row such that the number of hyper-terminals is minimized. ? 1 2 1 5 2 5 4 3 4 3 5 Can you give a solution for this instance?

MSOP Case 1: M(i, j) = ??? Case 2: Can be solved by dynamic programming. Consider the sub-problem from column i to j. Let M(i, j) be the maximum reduction in the number of hyper-terminals from i to j. i i+1 j No nets at i or the net is not connected to [i,j] Net p p1 p2 Case 1: M(i, j) = ??? Case 2:

MSOP No nets at i or the net is not connected to [i, j] Case 1: Net p p1 p2 Case 1: M(i, j) = ??? Case 2: Putting the two cases together: M(i, j) = ???

MSOP Algorithm For i = 1 to n M(i, i) = 0; For j = ?? to ?? Let n be the total number of pins on the row. MSOP algorithm: For i = 1 to n M(i, i) = 0; For j = ?? to ?? For i = ?? to ?? Compute M(i, i+j) Return M(1, n)

Runtime of MSOP Let n be the total number of columns. For each (i, j), M(i, j) can be found in O(?) time. There are O(n2) pairs of (i, j). So: Total time = O(?)

Selection of Net Segment Need to determine which terminal within a hyper-terminal to be used in the subsequent channel routing. Can be transformed to a special spanning forest problem. 1 1 Pick one out of four 1 1

Connectivity Graph 31 32 33 a connected component column A weighted multi-graph. Each hyper-terminal is represented by a vertex and each net is re-presented by a connected component. [8,10] 31 32 33 a connected component 2 1 5 4 3 6 7 8 9 10 11 Take net 3 as an example: column [6,8] [8,10] [8,11] [6,10] [10,10] [10,11]

Minimum Density Spanning Forest Problem (MDSFP) Want to connect hyper-terminals of the same net together. That is, finding a spanning tree for each connected component, or finding a spanning forest for the whole connectivity graph. The goal is to minimize the channel density. This problem is NP-Complete. Efficient heuristic is proposed.

Heuristic for MDSFP For each edge e, let r(e) = d(e)/D, where d(e) is the density of the interval associated with edge e and D is density of the whole channel. r(e) measures the relative degree of congestion over the interval associated with e. The heuristics repeatedly removes edges of high r() from the connectivity graph until a spanning forest is obtained. The value of r(e) for each edge e is updated after each removal.

Via Minimization In VLSI fabrication, the yield is inversely related to the number of vias. Every via has an associated resistance that affects the circuit performance. The size of a via is usually larger than the width of a wire. As a result, more vias will lead to more routing space.

Two Different Problems Constrained Via Minimization (CVM) Unconstrained Via Minimization (UVM)

Constrained Via Minimization (CVM) Given a detailed routing solution, minimize the number of vias by assigning wire segments to different layers. Vias occur only at the turning points. Also called the Layer Assignment Problem. 2 3 4 5 1 2 3 4 5 1

Unconstrained Via Minimization (UVM) Minimize the number of vias during routing. Vias can occur anywhere as needed. Consider an unreserved layer model for routing (both vertical and horizontal wires can be routed on the same layer in each region).

Topological Routing Topological Routing Geometric Mapping UVM is also known as Topological Routing. Topological Routing Geometric Mapping

CVM and UVM UVM is less popular than CVM since via minimization is usually considered secondary. Minimization of channel width, completion of routing, and minimization of total wirelength are considered more important. Note: modern routers usually will follow “preferred” layers. So via minimization essentially is to minimize the number of “bends”. We will show CVM just to illustrate some algorithmic aspects of via minimization.

CVM by Reduction to Maximum Cut Problem “Optimal Layer Assignment for Interconnect”, R. Y. Pinter, IEEE Int’l Conf. Circuits and Computers, pages 398-401, Sept. 1982.

Overview For two routing layers. Partition the routing region into clusters such that no “junction” is of degree more than 3. The problem can be transformed to finding a maximum cut in a graph.

Cluster Graph Representation 1 2 3 4 5 4 S1 S2 S6 S3 S4 S5 S7 h1 h2 h3 h5 h7 h8 Cluster Graph 2 1 3 5 S1 Cluster 1 2 3 4 5 4 S3 S4 S2 h7 h3 h4 h6 S5 h8 h1 h2 h5 S6 S7 Via 2 1 3 5

Layer Assignment Class C1: Horizontal wires on layer 1 In every cluster, there are only two possible ways to assign layers. Class C1: Horizontal wires on layer 1 Vertical wires on layer 2 Class C2: Horizontal wires on layer 2 Vertical wires on layer 1

Assign Clusters to C1 and C2 If two adjacent clusters are in the same class, the via candidates joining them are needed. If two adjacent clusters are in different classes, the vias candidates joining them are not needed. Same Class Different Classes C2 C2 C2 C1

Example of Class Assignment Cluster Graph S1 S3 h7 C1 h1 h3 S4 C2 S2 C2 S5 C1 S6 C1 h5 h2 S7 h8 1 2 3 4 5 4 S3 S4 h7 Original: 8 vias This solution: 4 vias S1 h3 h4 h6 S2 S5 h8 h1 h2 h5 S6 S7 2 1 3 5

Example of Class Assignment h7 A better solution: C2 h1 h3 S4 C1 S2 C1 S5 C2 S6 C2 h5 h2 S7 h8 2 3 4 5 1 S6 h1 h2 h3 h4 h5 h6 h7 h8 S1 S2 S3 S4 S5 S7 Optimal Solution: 2 vias

Class Assignment Problem No. of vias = No. of via candidates – No. of edges connecting a vertex in C1 and a vertex in C2 S1 S2 S6 S3 S4 S5 S7 C1 C2 Optimal Solution S1 S2 S6 S3 S4 S5 S7 C1 C2 No. of edges here = no. of vias that can be eliminated

Maximum Cut Problem A cut Maximum cut = A cut with the maxi- The layer assignment problem is equivalent to the Maximum Cut Problem of a graph. The Maximum Cut Problem is NP-Complete for general graphs. Solvable in polynomial time for planar graphs. [Hadlock 1975, SIAM Journal on Computing] Cluster graphs are planar. A cut Maximum cut = A cut with the maxi- mum no. of edges

Other Routing Issues Gridless Routing Multi-level routing DSM effects

Gridless Detailed Routing Gridless Routing More flexible Longer runtime due to complex data structure Gridless Detailed Routing Algorithms Shape (Tile) based routing [Sato, et al., ISCS87, Margarino, et al., TCAD87, Dion, et al., WRL Research Report 95/3, Liu, et al., ISPD98] Graph-based routing [Wu, et al., TC87, Ohtsuki, ICCAS85, Cong, et al., Zheng, et al., TCAD96, ICCAD’99] Subgrid routing [US Patent, 6,507,941 B1, Jan. 2003]

Multilevel Routing Framework (MARS [TCAD05]) Detailed routing Fine routing tile generation Implicit graph gridless routing G0 G0 G1 G1 Gk Coarsening Refinement History-based iterative refinement This is the framework of MARS. It is a very typical “v” shaped multilevel optimization framework with a downward coarsening pass and an upward refinement pass. The circuit is first partitioned into small tiles. At every coarsening level, the tiles are coarsened, and a sub-problem of the original routing problem is derived at that level. The actual routing process starts at the coarsest level, and then the results are refined at every level. We can also see this as the sub-problem at each level is solved with the guide from the previous result. Because of this hierarchical structure, MARS is more scalable. Also, multilevel framework provides a framework of integrating different optimization algrorithms at different levels. In MARS, a MCF-based routing algorithm is used in initial routing, a history based iterative refinement is used in refinement levels, and a gridless detailed router with implicit routing graph is used at the finest level. Multicommodity flow based algorithm Initial routing [Courtesy Prof. Jason Cong]

DSM Considerations Antenna effects Crosstalk noise Interconnect optimization & planning Manufacturability …… Will be covered in EE382V, Optimization Issues in VLSI CAD