Introduction (4541.633A SoC Design Automation) School of EECS Seoul National University This class is mainly on the design of embedded system on a chip. Now, as an introduction, I’ll give you an idea about what is an embedded system and what is the concerns and trends regarding the design of such a system on chip or so called SoC.

SoC Embedded systems SoC What is an embedded system?                                                                                                                 What is an embedded system? There is no clear definition of an embedded system. But one of the most widely accepted definition is that an embedded system is a system containing programmable processors or computers embedded in it, but which itself is not a computer. A cellular phone is a representative embedded system. A car is also an embedded system. Why? it has many microprocessors in it. High-end car has about 50 microprocessors in it. Is a car a mechanical system or electronic system? Soon the cost of electronics of a car will reach 50% of the total cost. Toys, robots, camcorders, pdas,... most of the electronic systems in our life are embedded systems.

3G mobile communication (CDMA2000) SoC 3G mobile communication (CDMA2000) This is a typical 3G mobile communication device. It consists of several chips. This chip has all digital components integrated in it. It has a PLL for clock generation, serial link, ADC, DAC, microprocessor, DSP for voice codec, CDMA modem, logic for testing, etc. The issue here is that how to design such embedded soc and what are the concerns.

What is SoC? System on Chip, System on a Chip A monolithic integrated circuit that contains all or most of the necessary circuits including microprocessors that make up a system Integrating the system functionalities on a single chip realizes benefits in terms of cost, performance, power consumption, reliability, etc. This is a typical 3G mobile communication device. It consists of several chips. This chip has all digital components integrated in it. It has a PLL for clock generation, serial link, ADC, DAC, microprocessor, DSP for voice codec, CDMA modem, logic for testing, etc. The issue here is that how to design such embedded soc and what are the concerns.

Why SoC? Performance Power consumption Reliability Cost (number of components) Form factor ... This is a typical 3G mobile communication device. It consists of several chips. This chip has all digital components integrated in it. It has a PLL for clock generation, serial link, ADC, DAC, microprocessor, DSP for voice codec, CDMA modem, logic for testing, etc. The issue here is that how to design such embedded soc and what are the concerns.

Challenges Time-to-market Technology Cost (development cost) SoC Challenges Time-to-market Technology Cost (development cost) Testability ... What are the major factors to be considered for the design of an embedded SoC? The most important factor is TTM. In other words, you must design and sell it faster than others or you lose. I’ll explain this in the following slides. The technology advances rapidly and there are lots of challenges. Leveraging on the advances in the technology, we must be able to satisfy the ever-increasing performance need. Power consumption is another important issue. Reliability, ... Cost is still an important issue. Chip area is the most concern in our case.

Microprocessor performance and clock frequency Clock frequency increase due to the advancement of semiconductor technology Additional MIPS increase due to the advancement of computer architecture

Power consumption in CMOS circuits Why low power? High performance and integrity of VLSI circuits Popularity of portable devices Power consumption in CMOS circuits Dynamic power dissipation (dominant) Short-circuit power dissipation Leakage power dissipation Dynamic power dissipation

Supply voltage reduction Power Consumption Supply voltage reduction Quadratic effect of voltage scaling on power 5V --> 3.3V => 60% power reduction Supply voltage reduction => increased latency Vdd energy/delay 5 1 Vdd energy 5 1 delay Vdd 5 1

Product life time vs. development time Time-to-Market Time-to-Market Product life time vs. development time Product life time decreases. New model development in every one or two years Complexity increases. The crisis here is that we must start designing a new model before we complete designing the previous model. So you must have many design teams: one for this year, one for next year, etc. This requires a lot of design resources and therefore a lot of design cost.

Revenue and time-to-market This slide shows a simple model of product life cycle. First introduction of the product  revenue increases as the product becomes popular  then it decreases as the time approaches the end of the cycle. The area under this curve represents the total revenue. It we introduce our product later than the first one by d, then we lose this much revenue compared to our competitor. For example, assume that the life cycle time is 2 years. Then w is 1 year. ...

Memory capacity quadrupled every three years Technology Technology Memory capacity quadrupled every three years Moore’s law Exponential People work harder and harder

Problems with deep sub-micron design Technology Problems with deep sub-micron design Thin wire Large interconnect delay delay  (wire length)2 Al --> Cu Such technology advancement has many challenges. source: ITRS 2003

Design Methodology Hardware design As the complexity increases, initial design moves toward more abstract levels Top-down design Behavioral-level design --> Architecture synthesis tool RT-level design --> Logic synthesis tool Gate-level design: Layout synthesis tool (P&R) Top-down + bottom-up (Synthesis with libraries) module DIFFEQ (x, y, u, dx, a, clock, start); input [7:0] a, dx; inout [7:0] x, y, u; input clock, start; reg [7:0] xl, ul, yl; always begin wait (start); while (x < a) xl = x +dx; ul = u - (3*x*u*dx) - (3*y*dx); yl = y + (u*dx); @(posedge clock); x = xl; u = ul; y = yl; end endmodule * +, -, < + control Before we discuss about systems design, let’s think about hw design. R D Q

Architecture Synthesis Register-Transfer-Level Design Methodology Hardware design flow example Functional Spec HDL Coding Simulation Behavioral-Level Architecture Synthesis Register-Transfer-Level Logic Synthesis Gate-Level ... The probability for the 1st chip to work? ... more than 90% You must keep it that way. Otherwise you will be in trouble. Why? The reason is mainly two fold. The most important reason is TTM. Each turn around time takes several months. Second reason is the cost. The fab costs million dollars for a deep submicron design. Back Annotation Layout Synthesis Layout

Software design Paradigm shift toward software Design Methodology Software design Paradigm shift toward software Microprocessor performance rapidly increases Flexibility, upgradability Low cost Microprocessor, microcontroller, DSP, ASIP Design challenges Parallel programming Software development for MP-SoC Partitioning for load balancing, communication overhead, ... Code optimization Minimization of memory size Maximization of performance Minimization of power consumption Real-time constraints Hard real-time (worst case performance) Soft real-time (probabilistic performance) No real-time (average case performance) The design cost of an embedded soc is now about half and half.

Hardware-Software Co-Design Design Methodology Hardware-Software Co-Design Balancing Performance of customized HW units Programmability of low cost SW components performance hardware HW-SW codesign performance constraint Since an embedded system consists of both hw and sw, we need to devise an efficient hw-sw codesign methodology. software cost cost constraint

hardware design integration software design hardware design Design Methodology Reduction of design time integration hardware design software design hardware design software design integration hardware design integration software design time

IP/Platform-Based Design Design Methodology IP/Platform-Based Design Complexity vs. productivity Complexity Productivity Complexity 58%/yr growth rate Productivity 21%/yr growth rate

Programmable video operations, DCT, IDCT, motion estimation Design Methodology Reuse of IPs DSP core 1 (D950) Modem ASIP 4 (VLIW DSP) Programmable video operations, standard extensions A/D & D/A DSP core 2 (D950) Sound High-speed HW Video operations for DCT, IDCT, motion estimation ASIP 1 Master Control ASIP 2 Memory Controller Memory Video RAM Glue logic I/O S interface ASIP 3 Bit Manipulation I/O Host interface

EDA ... Tools IP-based design Design Methodology Hard IP Soft IP Others ... EDA Tools

Application specific integration platform Design Methodology Platform-based design Soft IP EDA Tools Hard IP EDA Integrator Others EDA Tools Application specific integration platform Derivative

Application in C Design Methodology for(i = 0; i < 18; i++) { s = (mpfloat)0.0f; k = 0; do { s += X[k] * v[k]; s += X[k+1] * v[k+1]; s += X[k+2] * v[k+2]; s += X[k+3] * v[k+3]; s += X[k+4] * v[k+4]; s += X[k+5] * v[k+5]; k += 6; } while(k < 18); v += 18; ISCALE(s); t[i] = s; } /* correct the transform into the 18x36 IMDCT we need */ /* 36 muls */ for(i = 0; i < 9; i++) { x[i] = t[i+9] * Granule_imdct_win[gr->block_type][i]; ISCALE(x[i]); x[i+9] = t[17-i] * Granule_imdct_win[gr->block_type][i+9]; ISCALE(x[i+9]); x[i+18] = t[8-i] * Granule_imdct_win[gr->block_type][i+18]; ISCALE(x[i+18]); x[i+27] = t[i] * Granule_imdct_win[gr->block_type][i+27]; ISCALE(x[i+27]); }

Programmable video operations, DCT, IDCT, motion estimation Design Methodology Platform DSP core 1 (D950) Modem ASIP 4 (VLIW DSP) Programmable video operations, standard extensions A/D & D/A DSP core 2 (D950) Sound High-speed HW Video operations for DCT, IDCT, motion estimation ASIP 1 Master Control ASIP 2 Memory Controller Memory Video RAM Glue logic I/O S interface ASIP 3 Bit Manipulation I/O Host interface

Platform-based system design methodology Application Architecture Constraints Mapping Estimation of performance, area, and power in HW and SW Mapping results SW synthesis IF synthesis HW synthesis SW HW

Digital systems design Analog, mixed signal, A/D, D/A, RF, ... Related Fields Related Fields Digital systems design Analog, mixed signal, A/D, D/A, RF, ... Mechanical components, sensors, actuators, ... VLSI CAD synthesis (high-level, logic, layout), simulation, ... Software engineering software specification, generation, ... Distributed system design networks of communicating processors, ... Real-time systems design timing constraint (hard real-time, soft real-time), ... OS, compiler, computer architecture, ...

System specification and modeling Major Issues Major Issues System specification and modeling Languages, graphical representations, intermediate forms, models of computation, ... MP-SoC architecture design Processors design, communication network design, memory hierarchy, reconfigurable computing, ... SOC design methodology Partitioning, cosynthesis, cosimulation, emulation, prototyping, reusability, VDSM issues, interface and standardization, testing, ... Code generation and optimization Retargetable compiler, memory issues, execution time estimation, ... Low power system design System-level power management, bus coding, dynamic voltage scaling, ...