ECE2030 Introduction to Computer Engineering Lecture 14: Sequential Logic Circuits Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech

Sequential Logic Circuits Combinational circuits inputs outputs Storage Element delay Next State Present State Controller by a periodic clock or an event trigger Sequential circuits Combinational logic circuits State information (stored in memory) Output is a function of inputs and present state Can be synchronous or asynchronous

State machine example A TV channel control 1 CH 2 CH 3 1 1 CH 1

Sequential Logic Circuits outputs inputs Combinational circuits Next State Present State Storage Element clock Synchronous Circuits use clock pulse to synchronize For a typical synchronous design, data are latched into the storage upon clock transition (edge-triggered)

Closed-Loop Logic for Storing Information 1 Tpd Tpd A buffer

SR Latch QN S Q R

SR Latch R Q QN S S R Q QN 1 Reset Set Undefined No Change

SR Latch S Q QN R S R Q QN 1 Reset Set Undefined No Change

SR Latch w/ Control S Q C QN R C S R Q QN X 1 Reset Set Undefined X 1 Reset Set Undefined No Change

Issue of an SR Latch or SR Latch Q QN 1 Q QN S S R Q Race, and Unstable QN

D Latch D Q C QN C D Q QN X 1

D Latch  Keeping Data for Read Q Q

D Latch  Writing Data D Q D Q

10T D Latch w/ Transmission Gates En En Q D Q En

10T D Latch w/ Transmission Gates En=1 En D Q D D Q D En Writing Data

10T D Latch w/ Transmission Gates En=0 En D Q D D_new Q D En Writing Data

D Latch Symbol En D Q X NC 1 D Q En Q NC: No Change

Latch is Transparent D Latch is called “transparent” or “level sensitive” Output follows input instantaneously En D Q Q Transparent

Transparency Property D Q Transparent Latch En D En Q Storage Cell D En Q Storage Cell 1 Latch acts like a Wire

Problem of Transparency Other Logic Circuits D Q Transparent Latch En A momentary input change tunnels through the latch and the entire circuitry What problem this can cause?

Problem of Transparency D Q D Transparent Latch En 1 En D Q Oscillating  Unstable Unstable

Eliminating Transparency D Q D Q Transparent Latch Transparent Latch En En Separating the input and output, so they are independently controlled Only open one gate at a time to avoid tunneling

Behavior of Master-Slave Latches D Q D Q Storage Cell Storage Cell (0) 1 En En D Q D Q Storage Cell (1) Storage Cell En En 1

Behavior of Master-Slave Latches D1 Q1 D2 Q2 D1 En En En D1 (initialized to1) Q1=D2 Q2 A Toggle Cell, will discuss more later

Behavior of Master-Slave Latches D1 Q1 D2 Q2 En En En D1 (input) Q1=D2 Q2

Behavior of Master-Slave Latches D1 Q1 D2 Q2 En En En D1 (input) Q1=D2 Q2

Flip-Flop (F/F) D1 Q1 D2 Q2 1-bit Flip Flop Input Output Enable (or clock) 1-bit Flip Flop Input Output Enable (or clock)

Negative Edge Triggered Flip-Flop Input Output D1 Q1 D2 Q2 Enable (or clock) clock Input Q1=D2 Output

Positive Edge Triggered Flip-Flop Input Output D1 Q1 D2 Q2 Enable (or clock) clock Input Q1=D2 Output

Positive Edge Triggered Flip-Flop Input Output D1 Q1 D2 Q2 Enable (or clock) clock Input Q1=D2 Output

Flip Flops Symbols Positive Edge Triggered Negative Edge Triggered Q D Q C Q C Q Positive Edge Triggered D Flip Flop Negative Edge Triggered D Flip Flop

Dual-phase Non-overlapped Clocks In reality, enable control is not ideal Use dual phase clocks (1 and 2) to replace Enable and its inversion 1 Q1=D2 Input Output 2 D2 follows 1 while Output follows 2

Dual-Phase Non-overlapped Clocks Input Output D1 Q1 D2 Q2 1 2 1-bit Flip Flop Input Output 1 2