SmartCell: A Coarse-Grained Reconfigurable Architecture for High Performance and Low Power Embedded Computing Xinming Huang Depart. Of Electrical and Computer Engineering Worcester Polytechnic Institute xhuang@wpi.edu High Performance Embedded Computing Workshop MIT Lincoln Laboratory 19th September 2007 X. M. Huang SMART CELLS - dynamically reconfigurable microsystems with kilo-processors

Architecture overview Thousands of pico-processors interconnected with high-speed switching fabrics within a single chip Goal: low-power, high-performance, reconfigurable, and applicable X + Configurable interconnects PE11 PE12 PE10 PE9 SRM PE7 PE8 PE6 PE5 PE3 PE4 PE2 PE1 PE15 PE16 PE14 PE13 PE19 PE20 PE18 PE17 PE23 PE24 PE22 PE21 High Speed Data I/O (10s Gbps) inter-chip wireless radio X. M. Huang SMART CELLS - dynamically reconfigurable microsystems with kilo-processors

Technical Challenges, and Applications Performance Metrics, Technical Challenges, and Applications Performance/Power (GOPS/Watt) Applicability Flexibility ASIC GPGPU FPGA SmartCell Technical Challenges: Low power core functions Interconnections (wiring and routing) Compiler (hardware/alg co-design) Reliability (evolvable algorithms) For Defense and Space Applications Technology High Perform-ance Low Power Program-mable Applic-able Evolvable (Self-healing) FPGA Y N CPU/DSP GPU ASIC SmartCell Applications: low-power cognitive radio, space-time adaptive processing, imaging for manned or unmanned airborne, radar signal processing, target recognition and tracking, satellite on-board processing, biochemical sensing Trade off: power, performance, reconfigurability, and applicability (the cores are geared up for military applications with minimum number of transistor – tiny ASIC with programmable registers) Advantages: turn-off PEs in quiescent mode (ASIC and GPU generally do not have much capacity in power management, CPU does) You got to explore some novel ideas on the architecture and algorithm side Why not commercial section? FPGA 73.5% high-end communication/networking market where power is not a constraint. They are not going to give away their fundamental shares – ASIC prototyping. Target Performance: 1,024 ALU core 100 MHz 500 mW 200 GOPS X. M. Huang SMART CELLS - dynamically reconfigurable microsystems with kilo-processors

Experimental Performance Energy efficiency perspectives Benchmark performance of FIR filters Performances of fully pipelined 16-tap FIR filter Dynamic Power Core Power Gate equivalent Smart-Cell 20.3 mW 21.7 mW 265 k FPGA 157.6 mW 232.6 mW 82 k 2 by 2 SmartCell implementation: TSMC 130 nm ASIC library; 1.33 mm2; >500 MHz operating freq.; 10~18 times more power efficient than FPGA implementations; X. M. Huang SMART CELLS - dynamically reconfigurable microsystems with kilo-processors