ADPCM Adaptive Differential Pulse Code Modulation

Slides:



Advertisements
Similar presentations
High Performance 32 Channel ADPCM Codec File Number Here ® LogiCORE Products.
Advertisements

Analogue to Digital Conversion (PCM and DM)
Design Goal Design an Analog-to-Digital Conversion chip to meet demands of high quality voice applications such as: Digital Telephony, Digital Hearing.
1 Audio Compression Techniques MUMT 611, January 2005 Assignment 2 Paul Kolesnik.
Idongesit Ebong (1-1) Jenna Fu (1-2) Bowei Gai (1-3) Syed Hussain (1-4) Jonathan Lee (1-5) Design Manager: Myron Kwai Overall Project Objective: Design.
Idongesit Ebong (1-1) Jenna Fu (1-2) Bowei Gai (1-3) Syed Hussain (1-4) Jonathan Lee (1-5) Design Manager: Myron Kwai Overall Project Objective: Design.
1 Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3) Avni Jhunjhunwala (W2-4) Presentation 12 MAD MAC th April, 2006 Short Final Presentation.
Noise Canceling in 1-D Data: Presentation #13 Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar M2 April 20 th, 2005 Short.
[M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Oct. 22 Overall Project Objective : Dynamic Control.
Parking Pal Presentation #8 Team M1: Anna Kochalko Chris Moody Hong Tuck Liew John Wu Team TA: Kartik Murthy October 22, 2007 Gate Level Layout Your digital.
Viterbi Decoder: Presentation #11 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 11: 12 th April 2004 Short Final Presentation.
Huffman Encoder Project. Howd - Zur Hung Eric Lai Wei Jie Lee Yu - Chiang Lee Design Manager: Jonathan P. Lee Huffman Encoder Project Final Presentation.
Spatial and Temporal Data Mining
Noise Canceling in 1-D Data: Presentation #10 Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar M2 Mar 28 rd, 2005 Chip Level.
Team W3: Anthony Marchetta Derek Ritchea David Roderick Adam Stoler Milestone 11: April 12th Short Final Presentation Overall Project Objective: Design.
EE2F1 Speech & Audio Technology Sept. 26, 2002 SLIDE 1 THE UNIVERSITY OF BIRMINGHAM ELECTRONIC, ELECTRICAL & COMPUTER ENGINEERING Digital Systems & Vision.
Design Goal Design an Analog-to-Digital Conversion chip to meet demands of high quality voice applications such as: Digital Telephony, Digital Hearing.
Design Goal Design an Analog-to-Digital Conversion chip to meet demands of high quality voice applications such as: Digital Telephony, Digital Hearing.
M3: The Pro-Diver 525 Kavita Arora (M3-1) Lisa Gentry (M3-2) Steven Wasik (M3-3) Karolina Werner (M3-4) Design Manager: Steven Beigelmacher Stage 11: Mini-
1 Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3) Avni Jhunjhunwala (W2-4) Presentation 5 MAD MAC nd February, 2006 Top Level Integration.
1 Design Goal Design an Analog-to-Digital Conversion chip to meet demands of high quality voice applications such as: Digital Telephony, Digital Hearing.
Team W3: Anthony Marchetta Derek Ritchea David Roderick Adam Stoler Milestone 9: March 31st Chip Level Simulatio Overall Project Objective: Design an Air-Fuel.
M2: Team Paradigm :: Pre-Final Presentation 2-D Discrete Cosine Transform Team Paradigm (Group M2): Tommy Taylor Brandon Hsiung Changshi Xiao Bongkwan.
Digital Voice Communication Link EE 413 – TEAM 2 April 21 st, 2005.
1 Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3) Avni Jhunjhunwala (W2-4) Presentation 10 MAD MAC th April, 2006 Top-Level Layout.
Team W1 Design Manager: Rebecca Miller 1. Bobby Colyer (W11) 2. Jeffrey Kuo (W12) 3. Myron Kwai (W13) 4. Shirlene Lim (W14) Stage VIII: March 24 th 2004.
High Dynamic Range Emeka Ezekwe M11 Christopher Thayer M12 Shabnam Aggarwal M13 Charles Fan M14 Manager: Matthew Russo 6/26/
1. 2 Farhan Mohamed Ali Jigar Vora Sonali Kapoor Avni Jhunjhunwala 1 st May, 2006 Final Presentation MAD MAC 525 Design Manager: Zack Menegakis Design.
1 Product Overview Voice Specific Analog-to-Digital Conversion Chip Meeting demands of high quality voice applications such as: Digital Telephony, Digital.
Team W3: Anthony Marchetta Derek Ritchea David Roderick Adam Stoler Milestone 5: Feb. 18 th Component Layout Overall Project Objective: Design an Air-Fuel.
[M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Oct. 20 Overall Project Objective : Dynamic Control.
Sprinkler Buddy Presentation #12: “Final Presentation Outline” 4/25/2007 Team M3 Kalyan Kommineni Kartik Murthy Panchalam Ramanujan Sasidhar Uppuluri Devesh.
Team W1 Design Manager: Rebecca Miller 1. Bobby Colyer (W11) 2. Jeffrey Kuo (W12) 3. Myron Kwai (W13) 4. Shirlene Lim (W14) Stage II: February 4 th 2004.
Team W1 Design Manager: Rebecca Miller 1. Bobby Colyer (W11) 2. Jeffrey Kuo (W12) 3. Myron Kwai (W13) 4. Shirlene Lim (W14) Stage II: 26 th January 2004.
Fundamental of Wireless Communications ELCT 332Fall C H A P T E R 6 SAMPLING AND ANALOG-TO-DIGITAL CONVERSION.
Team W1 Design Manager: Rebecca Miller 1. Bobby Colyer (W11) 2. Jeffrey Kuo (W12) 3. Myron Kwai (W13) 4. Shirlene Lim (W14) Stage III: February 9 h 2004.
1 GPS Waypoint Navigation Team M-2: Charles Norman (M2-1) Julio Segundo (M2-2) Nan Li (M2-3) Shanshan Ma (M2-4) Design Manager: Zack Menegakis Presentation.
Camera Auto Focus Group W1 Tom Goff Dave Hwang Kate Killfoile Greg Look Design Manager: Bowei Gai Final Presentation, April 30 th, 2007 Project Objective:
1 Error Detecting Adder Yugandhar Asmath Saikiran Vodela Pavan Polum Puneet Shrivastava Advisor: Dr. David W Parent 8 th May 2006.
Team W1 Design Manager: Rebecca Miller 1. Bobby Colyer (W11) 2. Jeffrey Kuo (W12) 3. Myron Kwai (W13) 4. Shirlene Lim (W14) Stage IV: February 18 h 2004.
1 Design Goal Design an Analog-to-Digital Conversion chip to meet demands of high quality voice applications such as: Digital Telephony, Digital Hearing.
Group M3 Jacob Thomas Nick Marwaha Craig LeVan Darren Shultz Project Manager: Zachary Menegakis April 20, 2005 MILESTONE 13 Short Final Presentation DSP.
EE2F1 Speech & Audio Technology Sept. 26, 2002 SLIDE 1 THE UNIVERSITY OF BIRMINGHAM ELECTRONIC, ELECTRICAL & COMPUTER ENGINEERING Digital Systems & Vision.
GODIAN MABINDAH RUTHERFORD UNUSI RICHARD MWANGI.  Differential coding operates by making numbers small. This is a major goal in compression technology:
DARPA Digital Audio Receiver, Processor and Amplifier Group Z James Cotton Bobak Nazer Ryan Verret.
LECTURE Copyright  1998, Texas Instruments Incorporated All Rights Reserved Encoding of Waveforms Encoding of Waveforms to Compress Information.
AUDIO COMPRESSION msccomputerscience.com. The process of digitizing audio signals is called PCM PCM involves sampling audio signal at minimum rate which.
Introduction to VLSI Design – Lec01. Chapter 1 Introduction to VLSI Design Lecture # 2 A Circuit Design Example.
CIS679: Multimedia Basics r Multimedia data type r Basic compression techniques.
Image Compression Supervised By: Mr.Nael Alian Student: Anwaar Ahmed Abu-AlQomboz ID: IT College “Multimedia”
Digital Audio III. Sound compression (I) Compression of sound data requires different techniques from those for graphical data Requirements are less stringent.
Low Power, High-Throughput AD Converters
Low Power, High-Throughput AD Converters
Fundamentals of Multimedia Chapter 6 Basics of Digital Audio Ze-Nian Li and Mark S. Drew 건국대학교 인터넷미디어공학부 임 창 훈.
C OMBINATIONAL L OGIC D ESIGN 1 Eng.Maha AlGubali.
Low Power, High-Throughput AD Converters
Howd - Zur Hung Eric Lai Wei Jie Lee Yu - Chiang Lee Design Manager: Jonathan P. Lee [M2] Huffman Encoder Project Presentation #3 February 7 th, 2007 Overall.
ECE 3130 Digital Electronics and Design
Digital Communications Chapter 13. Source Coding
ADPCM Adaptive Differential Pulse Code Modulation
ADPCM Adaptive Differential Pulse Code Modulation
Predictive Coding.
UNIT II.
Alpha Blending and Smoothing
Chapter 7.2: Layer 5: Compression
Subject Name: Digital Communication Subject Code:10EC61
FIGURE 4.1 Block diagram of combinational circuit
EE115C – Winter 2009 Digital Electronic Circuits
Electronics for Physicists
Govt. Polytechnic Dhangar(Fatehabad)
Presentation transcript:

ADPCM Adaptive Differential Pulse Code Modulation Team M4 Andrew Akindele Edward Shim James Lee Anthony Xu Project Objectives Stage 10 Short Final Presentation Design and implement an Adaptive DPCM Manager : Joe Bakker Date Apr. 14, 2003 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project ADPCM Overview Adaptive Differential Pulse Code Modulation (ADPCM) – Very popular waveform coding technique • Main application is Telecommunications – Speech compression for transmission, storage and reconstruction – Reduce the bit data rate while maintaining good voice quality – Technique can apply to all waveforms which need high-quality audio, image and modem data 18-525 Integrated Circuit Design Project

How it works? Adaptive Differential Pulse Code Modulation Assume neighboring audio samples are similar to each other Predict future samples based on previous samples Record only difference between actual samples and predicted values Lossy compression 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Where Is It Used? Image compression JPEG MPEG Audio compression WAV Advantages over PCM 18-525 Integrated Circuit Design Project

Example Application (1) Digital Voicemail phone system 18-525 Integrated Circuit Design Project

Example Application (2) DECT Phone System 18-525 Integrated Circuit Design Project

Our Chosen Application Application: compression of audio data for telecommunications Output Bandwidth: OC3 (155 Mbps) Clock: 155Mbps/4bits = 38.75Mhz 18-525 Integrated Circuit Design Project

Algorithm Description Step Size Table [89] = [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 21, 23, 25, 28, 31, 34, 37, 41, 45, 50, 130, 143, 157, 173, 190, 209, 230, 253, 279, 307, 337, 371, 408, 449, 494, 544, 598, 658, 724, 796, 876, 963, 1060, 1166, 1282, 1411, 1552, 1707, 1878, 2066, 2272, 2499, 2499, 2749, 3024, 3327, 3660, 4026, 4428, 4871, 5358, 5894, 6484, 7132, 7845, 8630, 9493, 10442, 11487, 12635, 13899, 15289, 16818, 18500, 20350, 22385, 24623, 27086, 29794, 32767] indexTable [16] = [-1, -1, -1, -1, 2, 4, 6, 8, -1, -1, -1, -1, 2, 4, 6, 8] step size table index increment table 16 bit input 4 bit output C code: ftp://ftp.cwi.nl/pub/audio/adpcm.zip 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project ADPCM Features Operates on 16 bit values Constant 4:1 compression rate Quantized error output Adapts to rate of change in values C Code available at: ftp://ftp.cwi.nl/pub.audio/adpcm.zip 18-525 Integrated Circuit Design Project

Error (Output) Quantization Binary Numbers: 0101 = 0*23 + 1*22 + 0*21 + 1*20 = 5 ADPCM Error Output: 0101 = 1*(step) + 0*(step/2) + 1*(step/4) sign 18-525 Integrated Circuit Design Project

Algorithm Description Step 1: Difference Diff = Real Value - Predicted Value Step 2: Error and Prediction Generate error based on the step size and Diff Calculate change to Predicted Value using the step size and Diff Step 3: Step Size Change the index value depending on the error Change the step size using the index value 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project ADPCM Block Diagram 18-525 Integrated Circuit Design Project

Adaptation Example: Large Difference Increase Step Indata: 1000 ValPred: 0 Diff: 1000 Step: 7 Delta: 0 Indata: 1000 ValPred: 11 Diff: 989 Step: 16 Delta: 7 Indata: 1000 ValPred: 41 Diff: 959 Step: 34 Delta: 7 Indata: 1000 ValPred: 104 Diff: 896 Step: 73 Delta: 7 Indata: 1000 ValPred: 240 Diff: 760 Step: 157 Delta: 7 Indata: 1000 ValPred: 533 Diff: 467 Step: 337 Delta: 7 Indata: 1000 ValPred: 996 Diff: 4 Step: 494 Delta: 5 Indata: 1000 ValPred: 1057 Diff: 57 Step: 449 Delta: 0 Indata: 1000 ValPred: 1001 Diff: 1 Step: 408 Delta: 8 Indata: 1000 ValPred: 950 Diff: 50 Step: 371 Delta: 8 Small Difference Decrease Step 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Design Steps C and Verilog Coding Schematics Gate Level Layout Functional Block Layout Component Correction and Optimization Floorplanning Chip Level Layout Simulation and Optimization 18-525 Integrated Circuit Design Project

Major Design Decisions ROM table to store step size and index tables Carry Lookahead Adder No pipelining 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Initial Floorplan 18-525 Integrated Circuit Design Project

Detailed Floorplan (v.1) Dimensions: 500 x 480 18-525 Integrated Circuit Design Project

Detailed Floorplan (v.2) Dimensions: 450 x 480 18-525 Integrated Circuit Design Project

Detailed Floorplan (v.3) 18-525 Integrated Circuit Design Project

Road to Verification (1) 18-525 Integrated Circuit Design Project

Road to Verification (2) 18-525 Integrated Circuit Design Project

Road to Verification (3) 18-525 Integrated Circuit Design Project

Road to Verification (4) 18-525 Integrated Circuit Design Project

Road to Verification (5) 18-525 Integrated Circuit Design Project

Road to Verification (6) 18-525 Integrated Circuit Design Project

Road to Verification (7) 18-525 Integrated Circuit Design Project

Road to Verification (8) 18-525 Integrated Circuit Design Project

Road to Verification (9) 18-525 Integrated Circuit Design Project

Road to Verification (10) 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Issues Encountered 18-525 Integrated Circuit Design Project

Things to Look Out For In The Future 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Pin Specs 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Part Specs Part Name PMOS NMOS Transistors Width Height Area Density Versions 21mux-16bit-buffered 52 104 98.50 16.70 1644.95 0.0632 2 21mux-8bit-buffered 26 51.45 16.30 838.64 0.0620 1 ROMindex 14 32 46 27.60 28.35 782.46 0.0588 ROMstep 183 1672 1855 95.80 172.40 16515.92 0.1123 4 clamp_index 92 48.70 27.90 1358.73 0.0677 fsm 69 71 140 61.30 39.60 2427.48 0.0577 fulladder8 112 224 99.00 36.90 3653.10 0.0613 tspcdffw16 156 172 328 148.40 28.70 4259.08 0.0770 3 tspcdffw8 78 86 164 62.50 1793.75 0.0914 tspcdff16 120 76.10 39.15 2979.32 0.0752 tspcdff8 60 38.00 35.40 1345.20 0.0833 16bitadder 472 944 157.30 89.90 14141.27 0.0668 6 16bitsub 488 976 158.55 14253.65 0.0685 16bitaddsub 540 1080 159.75 106.10 16949.48 0.0637 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Part Specs (cont) Part Name PMOS NMOS Transistors Width Height Area Density Versions error_vpdiff_macro1 1153 2306 341.30 110.15 37594.20 0.0613 7 error_vpdiff_macro2 325.60 103.90 33829.84 0.0682 3 error_vpdiff_macro3 1069 2138 324.90 33757.11 0.0633 macro_right_1 461 495 956 132.60 159.40 21136.44 0.0452 1 macro_right_2 547 2070 2617 198.20 172.40 34169.68 0.0766 2 macro_right_3 786 840 1626 202.00 171.70 34683.40 0.0469 fullschematic_lhs 4435 8870 317.90 432.10 137364.59 0.0646 6 fullschematic_rhs 1806 3409 5215 221.95 461.65 102463.22 0.0509 FULL SCHEMATIC 6249 7852 14101 547.75 466.05 255278.89 0.0552 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Layer Mask (Active) 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Layer Mask (Poly) 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Layer Mask (Metal1) 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Layer Mask (Metal2) 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Layer Mask (Metal3) 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Layer Mask (Metal4) 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Full Chip Layout 18-525 Integrated Circuit Design Project

Full Chip with Overlaid Floorplan 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Conclusions 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Emulations (1) 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Emulations (2) 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Status Finish up empty slides Work on Final Paper 18-525 Integrated Circuit Design Project