TDCB status Jacopo Pinzino, Stefano Venditti

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Presentation transcript:

TDCB status Jacopo Pinzino, Stefano Venditti NA62 collaboration meeting Siena – 30/08/2012

Outline New firmware, new features New TDCBs (V6) tested and distributed Tests during the dry run Conclusions and todo list

New firmware The old firmware (written using the Quartus II editor) was rewritten using HDL designer and fully tested MOTIVATIONS Full SVN support Easier interface Possibility to test single blocks using Modelsim

New features PULSER FEATURES The pulser block allows to send signals to the front-end electronics through an ad-hoc LVDS pair in the connector. This can be used to trigger calibration pulses FEATURES 4 mode: one-shot, tel62 trigger, lemo cable, tdcb pulser Duty cycle and rate selection different for each connector (tdcb pulser) Pulse counter

New features TDC EMULATOR FEATURES An emulation of the TDC has been implemented inside the TDCB FPGA . In the emulation mode data is sent through the whole chain to the PPs, the data format being the same as the TDCs’. FEATURES Configurable number of words produced (up to 256 per TDC) Configurable signal length and distance between two signals the output is the same in each trigger (6.4 μs)

14 new TDCBs V6 arrived in Pisa on July 5° Minor changes wrt V5 (test point from each TDC added, connectors moved to avoid noise, some pins eliminated) Tour de force to test the boards before leaving for the dry run Several problems found (mainly due to unconnected resistor bunches on the board) FPGA-PP communication tested through fixed patterns (send by TDCs) TDC-FPGA communication tested using signals from a pattern generator Few noisy channels spotted (documented on Twiki) Boards ready the day before leaving

New TDCBs (V6)

BEWARE: bent or not properly plugged cables may produce noise! Dry run tests Tests using the front-end pulser triggered by the TDCB were performed for all requesting detectors The front-end was the same for all detectors (LAV FEE) except the CEDAR’s All signals from the front-end were seen in the first stages of the PP (which means that the TDCB is working fine) Number of signals from front-end counted in the TDCB→OK tests on larger rates (~1 MHz) and larger time scale needed (data on disk required) BEWARE: bent or not properly plugged cables may produce noise!

almost there… Conclusions Todo list The new firmware seems to work fine. Tests performed during the dry run were successful Todo list Write the controller for the onboard SRAM(ongoing,almost done) Improve/finalize the manual, make it more “human readable” Perform tests on a larger time scale (~ burst time) Write the TDCB article almost there…