TDCB status Jacopo Pinzino, Stefano Venditti

Slides:



Advertisements
Similar presentations
Status of the LAV electronics G. Corradi, C. Paglia, D. Tagnani F. Gonnella, M. Raggi INFN LNF F. Gonnella, M. Raggi INFN LNF Photon Veto WG CERN 13/12/2011.
Advertisements

20 Feb 2002Readout electronics1 Status of the readout design Paul Dauncey Imperial College Outline: Basic concept Features of proposal VFE interface issues.
DSP online algorithms for the ATLAS TileCal Read Out Drivers Cristobal Cuenca Almenar IFIC (University of Valencia-CSIC)
RPC Trigger ESR Warsaw 08 July 2003 F. Loddo I.N.F.N. Bari Status report on RPC FEB production Status report on RPC Distribution Board Interfaces RPC-LB.
Status of LAV FEE electronics G. Corradi, C. Paglia, D. Tagnani & M. Raggi, T. Spadaro, P. Valente.
Inter TEL62 communication M. Raggi, M. Piccini, F. Gonnella 16 th October 2013 TDAQ Working Group Meeting.
Status of the digital readout electronics Mauro Raggi and F. Gonnella LNF Photon Veto WG CERN 13/12/2011.
Readout electronics for the MUV detectors R. Fantechi 28/3/2012.
Leo Greiner IPHC meeting HFT PIXEL DAQ Prototype Testing.
AHCAL electronics. Status and Outlook Peter Göttlicher for the AHCAL developers CALICE meeting UT Arlington, March 11th, 2010.
1 “Fast FPGA-based trigger and data acquisition system for the CERN experiment NA62: architecture and algorithms” Authors G. Collazuol(a), S. Galeotti(b),
15 October 2013 CHANTI Status Report F. Ambrosino, T. Capussela, D. Di Filippo, P. Massarotti, M. Mirra, M. Napolitano, L. Roscilli, G. Saracino Università.
Local Trigger Unit (LTU) status T. Blažek, V. Černý, M. Kovaľ, R. Lietava Comenius University, Bratislava M. Krivda University of Birmingham 30/08/2012.
HBD FEM the block diagram preamp – FEM cable Status Stuffs need to be decided….
“TDAQ for 2012 runs” Gianluca Lamanna (CERN) Annual review meeting
Muon Electronics Upgrade Present architecture Remarks Present scenario Alternative scenario 1 The Muon Group.
C. Combaret DIF_GDIF_MDIF_D ASU 6x 24 HR2 ASU USB Hub RPi USB2 DCC SDCC RPi USB 1 hub+Rpi for 4 cassettes 1 DCC for 8 cassettes (1 spare) Trigger.
HBD FEE test result summary + production schedule 16mv test pulse result –5X attenuator + 20:1 resistor divider at input (to reduce the noise on the test.
Status and Improvements of TDCB project TDAQ working group meeting Andrea Burato (INFN Pisa) On behalf of TDCB working group.
FVTX Electronics (WBS 1.5.2, 1.5.3) Sergey Butsyk University of New Mexico Sergey Butsyk DOE FVTX review
TELL-1 and TDC board: present status and future plans B. Angelucci, A. Burato, S. Venditti.
TDCB Status report Bruno Angelucci, Stefano Venditti NA62 meeting, 14/12/2011.
Overview, remarks, lamentations, hope and despair M. Sozzi TDAQ WG meeting CERN - 4 June 2013 Introduction, news and appetizer.
March 9, 2005 HBD CDR Review 1 HBD Electronics Preamp/cable driver on the detector. –Specification –Schematics –Test result Rest of the electronics chain.
The Patti Board Gianluca Lamanna (INFNPisa) TEL62 workshop – Pisa –
12 September 2006Silicon Strip Detector Readout Module J. Hoffmann SIDEREM SIlicon Strip DEtector REadout Module.
“Planning for Dry Run: material for discussion” Gianluca Lamanna (CERN) TDAQ meeting
TEL62 AND TDCB UPDATE JACOPO PINZINO ROBERTO PIANDANI CERN ON BEHALF OF PISA GROUP 14/10/2015.
Mu2e NA62 TEL62 & TDCB repairs Radiation effects in TEL62 Franco Spinella 16/12/2015.
NA 62 TTC partition timing T.Blažek, V.Černý, R.Lietava, M.Kovaľ, M.Krivda Bratislava, Birmingham We are developing procedures for timing parameter adjustment.
TELL1 readout in RICH test: status report Gianluca Lamanna on behalf of TDAQ Pisa Group (B.Angelucci, C.Avanzini, G.Collazuol, S.Galeotti, G.L., G.Magazzu’,
“TALK board status” R.Fantechi, G.Lamanna & D.Gigi (CERN)
Evelyn Thomson Ohio State University Page 1 XFT Status CDF Trigger Workshop, 17 August 2000 l XFT Hardware status l XFT Integration tests at B0, including:
Many LAV stations in digital trigger Francesco Gonnella Photon-Veto Working Group CERN – 03/02/2015.
Status of LAV electronics commissioning Mauro Raggi, Francesco Gonnella Laboratori Nazionali di Frascati 1 Mauro Raggi - Laboratori Nazionali di Frascati4.
1 Timing of the calorimeter monitoring signals 1.Introduction 2.LED trigger signal timing * propagation delay of the broadcast calibration command * calibration.
Sumary of the LKr WG R. Fantechi 31/8/2012. SLM readout restart First goal – Test the same configuration as in 2010 (rack TS) – All old power supplies.
V.Duk, INFN Perugia1 CHOD TDAQ status and rates Viacheslav Duk, INFN Perugia On behalf of the CHOD working group.
C.Beigbeder, D.Breton, M.El Berni, J.Maalmi, V.Tocut – LAL/In2p3/CNRS L.Leterrier, S. Drouet - LPC/In2p3/CNRS P. Vallerand - GANIL/CNRS/CEA SuperB -Collaboration.
SKIROC status Calice meeting – Kobe – 10/05/2007.
Development of new DAQ system at Super-Kamiokande for nearby supernova A.Orii T. Tomura, K. Okumura, M. Shiozawa, M. Nakahata, S. Nakayama, Y. Hayato for.
RICH Readout Plans F. Bucci, M. Piccini on behalf of the RICH WG.
Gianluca Lamanna TDAQ WG meeting. CHOD crossing point two slabs The CHOD offline time resolution can be obtained online exploiting hit position.
DCH FEE STATUS Level 1 Triggered Data Flow FEE Implementation &
The Totem trigger architecture The LONEG firmware archtecture
LAV front-end and readout status
AHCAL Beam Interface (BIF)
TDC Testing Status Edge Detector test for up to 7 hits per channel:
Firmware Structure Alireza Kokabi Mohsen Khakzad Friday 9 October 2015
DCH FEE 28 chs DCH prototype FEE &
Status of the Beam Phase and Intensity Monitor for LHCb
A New Clock Distribution/Topology Processor Module for KOTO (CDT)
ATLAS Local Trigger Processor
The University of Chicago
L0 processor for NA62 Marian Krivda 1) , Cristina Lazzeroni 1) , Roman Lietava 1)2) 1) University of Birmingham, UK 2) Comenius University, Bratislava,
Status of the Merlin Readout System
Testbeam Timing Issues.
DCH Electronics Upgrade: Overview and Status
Front-end electronic system for large area photomultipliers readout
8254 Timer and Counter (8254 IC).
University of California Los Angeles
Trigger system Marián Krivda (University of Birmingham)
M. Krivda for the ALICE trigger project, University of Birmingham, UK
STAR-CBM Joint Workshop Heidelberg, Physikalisches Institut
The New Trigger/GPS Module for the EEE Project
RPC Front End Electronics
Clock & Control Timing and Link 29 July 2008 Matt Warren Maurice Goodrick, Bart Hommels, Marc Kelly, ABSTRACT: A data acquisition system is described.
RPC Electronics Overall system diagram Current status At detector
Clock & Control Timing and Link 29 July 2008 Matt Warren Maurice Goodrick, Bart Hommels, Marc Kelly, ABSTRACT: A data acquisition system is described.
ASD-TDC joint test with MDT-CSM
Presentation transcript:

TDCB status Jacopo Pinzino, Stefano Venditti NA62 collaboration meeting Siena – 30/08/2012

Outline New firmware, new features New TDCBs (V6) tested and distributed Tests during the dry run Conclusions and todo list

New firmware The old firmware (written using the Quartus II editor) was rewritten using HDL designer and fully tested MOTIVATIONS Full SVN support Easier interface Possibility to test single blocks using Modelsim

New features PULSER FEATURES The pulser block allows to send signals to the front-end electronics through an ad-hoc LVDS pair in the connector. This can be used to trigger calibration pulses FEATURES 4 mode: one-shot, tel62 trigger, lemo cable, tdcb pulser Duty cycle and rate selection different for each connector (tdcb pulser) Pulse counter

New features TDC EMULATOR FEATURES An emulation of the TDC has been implemented inside the TDCB FPGA . In the emulation mode data is sent through the whole chain to the PPs, the data format being the same as the TDCs’. FEATURES Configurable number of words produced (up to 256 per TDC) Configurable signal length and distance between two signals the output is the same in each trigger (6.4 μs)

14 new TDCBs V6 arrived in Pisa on July 5° Minor changes wrt V5 (test point from each TDC added, connectors moved to avoid noise, some pins eliminated) Tour de force to test the boards before leaving for the dry run Several problems found (mainly due to unconnected resistor bunches on the board) FPGA-PP communication tested through fixed patterns (send by TDCs) TDC-FPGA communication tested using signals from a pattern generator Few noisy channels spotted (documented on Twiki) Boards ready the day before leaving

New TDCBs (V6)

BEWARE: bent or not properly plugged cables may produce noise! Dry run tests Tests using the front-end pulser triggered by the TDCB were performed for all requesting detectors The front-end was the same for all detectors (LAV FEE) except the CEDAR’s All signals from the front-end were seen in the first stages of the PP (which means that the TDCB is working fine) Number of signals from front-end counted in the TDCB→OK tests on larger rates (~1 MHz) and larger time scale needed (data on disk required) BEWARE: bent or not properly plugged cables may produce noise!

almost there… Conclusions Todo list The new firmware seems to work fine. Tests performed during the dry run were successful Todo list Write the controller for the onboard SRAM(ongoing,almost done) Improve/finalize the manual, make it more “human readable” Perform tests on a larger time scale (~ burst time) Write the TDCB article almost there…