Unit IV: GATE LEVEL DESIGN Parasitic Elements Unit IV: GATE LEVEL DESIGN VLSI DESIGN

Out Line Sheet Resistance Capacitance Delay Models (Elmore Delay ) 14/02/2009 VLSI Design

Introduction Wiring-Up of chip devices takes place through various conductors produced during processing Today, interconnects constitute the main source of delay in MOS circuits We will examine: Sheet Resistance – Resistance / Unit Area Area Capacitance Delay Units 14/02/2009 VLSI Design

The Wire schematics physical 14/02/2009 VLSI Design

Interconnect Impact on Chip 14/02/2009 VLSI Design

Wire Models Capacitance-only All-inclusive model 14/02/2009 VLSI Design

Impact of Interconnect Parasitics Reduce reliability Affect performance and power consumption Classes of parasitics Resistive Capacitive Inductive 14/02/2009 VLSI Design

Transistor source/drain parasitics Source/drain have significant capacitance, resistance. Measured same way as for wires. Source/drain R, C may be included in Spice model rather than as separate parasitics. 14/02/2009 VLSI Design

Resistance 14/02/2009 VLSI Design

Sheet Resistance A Resistance of a square slab of material RAB = ρL/A => R = ρL/(t*W) Let L = W (square slab) => RAB = ρ/t = Rs ohm / square t w L B RAB = ZRsh Z = L/W 14/02/2009 VLSI Design

Wire Resistance r = resistivity (W*m) R = sheet resistance (W/)  is a dimensionless unit(!) Count number of squares R = R * (# of squares)  R is completely independent of the area of the square. 1μm per side square slab of material has exactly the same resistance as a 1 cm per side square slab of the same material if the thickness is the same. 14/02/2009 VLSI Design

Wire Resistance 14/02/2009 VLSI Design

Resistor Resistors are made by doped silicon or polysilicon on an IC chip Resistance is determined by Length, line Width, Height, and Dopant concentration 14/02/2009 VLSI Design

Dealing with Resistance Selective Technology Scaling Use Better Interconnect Materials reduce average wire-length e.g. copper, silicides More Interconnect Layers A silicide is a compound that has silicon with more electropositive elements. Examples: nickel silicide, NiSi :sodium silicide, Na2Si ; magnesium silicide, Mg2Si Platinum silicide, PtSi ;Titanium silicide, TiSi2 ;Tungsten silicide, WSi2 14/02/2009 VLSI Design

Skin effect At low frequencies, most of copper conductor’s cross section carries current. As frequency increases, current moves to skin of conductor. Back EMF induces counter-current in body of conductor. Skin effect most important at gigahertz frequencies. 14/02/2009 VLSI Design

Skin effect, cont’d Isolated conductor: Conductor and ground: Low frequency Low frequency High frequency High frequency 14/02/2009 VLSI Design

Skin depth Skin depth is depth at which conductor’s current is reduced to 1/3 = 37% of surface value: d = 1/sqrt(p f m s) f = signal frequency m = magnetic permeability s = wire conducitvity 14/02/2009 VLSI Design

Effect on resistance Low frequency resistance of wire: Rdc = 1/ s wt High frequency resistance with skin effect: Rhf = 1/2 s d (w + t) Resistance per unit length: Rac = sqrt(Rdc 2 + k Rhf 2) Typically k = 1.2. 14/02/2009 VLSI Design

Contacts Resistance Contacts and vias also have 2-20 W Use many contacts for lower R Many small contacts for current crowding around periphery 14/02/2009 VLSI Design

Layer Rs (Ohm / Sq) Aluminium 0.03 N Diffusion 10 – 50 Silicide 2 – 4 Typical sheet resistance values for materials are very well characterised Layer Rs (Ohm / Sq) Aluminium 0.03 N Diffusion 10 – 50 Silicide 2 – 4 Polysilicon 15 - 100 N-transistor Channel 104 P-transistor Channel 2.5 x 104 14/02/2009 VLSI Design Typical Sheet Resistances for 5µm Technology

Sheet Resistance 14/02/2009 VLSI Design

Resistance Depends on resistivity of material r (Rho) Sheet resistance Rs = r /t see Table 2-4, p. 80 Resistance R = Rs * L / W Corner approximation - count a corner as half a square Example: R = Rs(poly) * 13 + 2*(1/2) + 3*(1/2) squares R = 4Ω/sq * 15.5 squares = 62Ω Corner (1/2 Square) 1/2 Square 1/2 Square Corner (1/2 Square) Corner (1/2 Square) 14/02/2009 VLSI Design

Compute Resistance Partition long wire into rectangles Count the number of squares ((l1/w1)+(l2/w2)+(l3/w3))Rs l1 w2 w1 l2 w3 l3 14/02/2009 VLSI Design

Modern Interconnect 14/02/2009 VLSI Design

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Example: Intel 0.25 micron Process 5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric 14/02/2009 VLSI Design

Layer Rs (Ohm / Sq) Aluminium 0.03 N Diffusion 10 – 50 Silicide 2 – 4 Typical sheet resistance values for materials are very well characterised Layer Rs (Ohm / Sq) Aluminium 0.03 N Diffusion 10 – 50 Silicide 2 – 4 Polysilicon 15 - 100 N-transistor Channel 104 P-transistor Channel 2.5 x 104 14/02/2009 VLSI Design Typical Sheet Resistances for 5µm Technology

N-type Minimum Feature Device Polysilicon L N - diffusion 2λ W Here ,Length to Width ratio ,denoted Z is (2/2)=1 2λ R = 1square x Rs Ohm / Square = Rs = 104Ώ 14/02/2009 VLSI Design

Polysilicon L = 8λ W = 2λ N - diffusion R = Z Rs R = (L/W) * Rs Here ,Length to Width ratio ,denoted Z is (8/2)=4 R = Z Rs R = (L/W) * Rs R = 4×104 Ώ 14/02/2009 VLSI Design

Exercise 1.Calculate ON resistance of the circuit shown from VDD to GND.If n-Channel sheet resistance Rsn=104 Ω per Square ,and P-channel sheet resistance Rsp=3.5×104 Ω per Square. Take CMOS Inverter as Circuit diagram.Given Zpu =1 and Zpd=1. . 14/02/2009 VLSI Design

Capacitance 14/02/2009 VLSI Design

Capacitors Charge storage device Memory Devices, esp. DRAM Challenge: reduce capacitor size while keeping the capacitance High-k dielectric materials 14/02/2009 VLSI Design

Capacitors Parallel plate Stacked Deep Trench Dielectric Layer Poly 2 Poly Si Si Poly Si Oxide Si Poly 1 Heavily Doped Si Parallel plate Stacked Deep Trench 14/02/2009 VLSI Design

Capacitance of Wire Interconnect 14/02/2009 VLSI Design

Interconnects - Capacitance Parallel Plate Capacitance L W H Dielectric Substrate tdi Keep in mind: C is proportional to the overlap between conductors C is inversely proportional to their separation 14/02/2009 VLSI Design

Permittivity 14/02/2009 VLSI Design

Area Capacitance of Layers Conducting layers are separated from each other by insulators (typically SiO2) This may constitute a parallel plate capacitor, C = є0єox A / D (farads) D = thickness of oxide, A = area, єox = 4 F/µm2 (SiO2) Area capacitance given in pF/µm2 14/02/2009 VLSI Design

Capacitance Value in pF×10-4 /µm2 (5μm Technology) Gate to Channel 4 Diffusion(Active) 1 Poly silicon to Substrate 0.4 Metal1 to substrate 0.3 Metal2 to substrate 0.2 Metal2 to metal 1 Metal2 to polysilicon 14/02/2009 VLSI Design

Capacitance Standard unit for a technology node is the gate - channel capacitance of the minimum sized transistor (2λ x 2λ), having W=L=feature Size ,given as Cg This is a ‘technology specific’ value 14/02/2009 VLSI Design

Cg may be evaluated for any MOS process Cg may be evaluated for any MOS process. For example ,for 5μm MOS Circuits Area/Standard square= 5μm × 5μm =25 μm2(=area of minimum size transistor) Capacitance value (From table)=4 ×10-4 pF/µm2 Thus Standard value Cg = 25 μm2 × 4 ×10-4 pF/µm2= 0.01 pF 1.Calculate the gate capacitance value of 5μm technology minimum sized transistor with gate to channel capacitance value is 8 ×10-4 pF/µm2 2.Calculate the gate capacitance value of 2μm technology minimum sized transistor with gate to channel capacitance value is 8 ×10-4 pF/µm2 14/02/2009 VLSI Design

Interconnects - Capacitance Fringing Capacitance Dielectric Substrate H Dielectric Substrate Cpp Cfr 14/02/2009 VLSI Design

Interconnects - Capacitance Total Capacitance Dielectric Substrate + H w Keep in mind: C is proportional to the overlap between conductors C is inversely proportional to their separation 14/02/2009 VLSI Design

Fringing Capacitance 14/02/2009 VLSI Design

Interwire Capacitance 14/02/2009 VLSI Design

Wiring Capacitances (0.25 mm CMOS) 14/02/2009 VLSI Design

Note that τ is very similar to channel transit time τsd Delay Unit For a feature size square gate, τ = Rs x Cg i.e for 5µm technology, τ = 104 ohm/sq x 0.01pF = 0.1ns Because of effects of parasitics which we have not considered in our model, delay is typically of the order of 0.2 - 0.3 ns Note that τ is very similar to channel transit time τsd One standard (feature size square) gate area capacitance being charged through one feature size square of n-channel resistance (that is,through Rs for an nMOS pass transistor channel ) as in the figure Time constant τ=(1 Rs (n channel) × 1Cg ) seconds 14/02/2009 VLSI Design

Interwire Capacitance Taken from “Digital Integrated Circuits”, 2nd Edition, Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic Copyright 2002 J. Rabaey et al. 14/02/2009 VLSI Design

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Interconnects - Inductance It can be evaluated with the aid of its definition: v=Ldi/dt It is possible to calculate the inductance from its geometry and its environment A simpler approach relies on the fact that the capacitance c and inductance l (per unit length) are related: cl=em (e and m are the permittivity and permeability of the surrounding dielectric) Caution: conductor must be surrounded by a uniform dielectric 14/02/2009 VLSI Design

Simplifications Inductive effects can be ignored if the resistance is substantial (e.g. a long Al wire with small cross-section) or if the rise and fall times of the applied signals are slow When the wires are short, the cross-section is large or the material has low-resistivity, a capacitance-only model can be used When the separation between neighboring wires is large or when wires only run together for a short distance, inter-wire capacitance can be ignored, and all the parasitic capacitance can be modeled as capacitance to ground 14/02/2009 VLSI Design

Electrical Wire Model Ideal Wire: Simplistic Useful for early phase of the design OK for small components, e.g. gates To study the effects of parasitics we need to model them 14/02/2009 VLSI Design

Electrical Wire Model Lumped vs Distributed 14/02/2009 VLSI Design

Electrical Wire Model – Lumped C If resistive component is small and switching frequencies are in the low to medium range, it makes sense to consider only capacitive component Wire still represents an equipotential region Only impact on performance is the loading effect Popular model C 14/02/2009 VLSI Design

Electrical Wire Model – Lumped RC If wire resistance is significant, a resistive-capacitive model is needed Lumped RC model is pessimistic and inaccurate for long interconnect wire Distributed rc-model is complex and no closed form solution exists Elmore delay formula: lumped RC comes to help R C 14/02/2009 VLSI Design

Electrical Wire Model – Lumped RC Elmore Delay s R2 C2 R4 C4 C3 R3 Ci Ri 1 2 3 4 i Consider an RC-tree: The network has a single input node All capacitors between node and ground The network does not contain any resistive loop 14/02/2009 VLSI Design

Electrical Wire Model – Lumped RC Elmore Delay s R2 C2 R4 C4 C3 R3 Ci Ri 1 2 3 4 i RC-tree property: Unique resistive path between the source node s and any other node i of the network  path resistance Rii Example: R44=R1+R3+R4 14/02/2009 VLSI Design

Electrical Wire Model – Lumped RC Elmore Delay s R2 C2 R4 C4 C3 R3 Ci Ri 1 2 3 4 i RC-tree property: Extended to shared path resistance Rik: Example: Ri4=R1+R3 Ri2=R1 14/02/2009 VLSI Design

Electrical Wire Model – Lumped RC Elmore Delay Assuming: Each node is initially discharged to ground A step input is applied at time t=0 at node s The Elmore delay at node i is: It is an approximation: it is equivalent to first-order time constant of the network Proven acceptable Powerful mechanism for a quick estimate 14/02/2009 VLSI Design

Electrical Wire Model – Lumped RC Elmore Delay Special case: RC-chain (or ladder) Shared-path resistance path resistance R1 C1 R2 C2 RN CN Vin VN 14/02/2009 VLSI Design

Interconnects – Why do we care? Technology scaling: miniaturization of devices (scale L, W, TOX, VTH) Device Scaling  Faster, smaller devices L[mm]=0.35, 0.25, 0.18, 0.12, etc  S0.7 Interconnect Scaling  Larger delays! Local interconnects: Almost constant Global interconnects:RC delay goes as 1/S or 1/S3 Also, parasitics give rise to a whole set of signal integrity issues  Design paradigm shift from device-centric to interconnect-centric 14/02/2009 VLSI Design

Interconnects – Why do we care? 14/02/2009 ITRS 2001 VLSI Design

New Interconnect Materials Aluminium  Copper Lower resistivity Higher immunity to Electromigration SiO2  Low-k dielectrics 14/02/2009 VLSI Design

What causes delay? In MOS circuits capacitive loading is the main cause Due to: Device capacitance Interconnect capacitance 14/02/2009 VLSI Design

MOSFET capacitances MOS capacitances have three origins: The basic MOS structure The channel charge The pn-junctions depletion regions 14/02/2009 VLSI Design

Channel capacitance The channel capacitance is nonlinear Its value depends on the operation region Its formed of three components: Cgb - gate-to-bulk capacitance Cgs - gate-to-source capacitance Cgd - gate-to-drain capacitance Operation region C gb gs gd Cutoff ox W L Linear (1/2) C Saturation (2/3) C 14/02/2009 VLSI Design

MOS structure capacitances Source/drain diffusion extend below the gate oxide by: xd - the lateral diffusion This gives origin to the source/drain overlap capacitances: Gate-bulk overlap capacitance: 14/02/2009 VLSI Design

Channel capacitance Cg = Weff  Leff  Cox Gate-to-bulk Gate-to-source Cg + Cgbo 2/3 Cg + Cgso Gate-to-bulk 1/2 Cg + Cgbo Cgdo , Cgso Cgbo Gate-to-source Gate-to-drain Off Saturated Linear 14/02/2009 VLSI Design

Junction capacitances Csb and Cdb and diffusion capacitances composed of: Bottom-plate capacitance: Side-wall capacitance: 14/02/2009 VLSI Design

Junction capacitances 0.24 mm process NMOS L(drawn) = 0.24 mm L(effective) = 0.18 mm W(drawn) = 2 mm Ls = 0.8 mm Cj (s, d) = 1.05 fF/mm2 Cjsw = 0.09 fF/mm Cbottom = 1.68 fF Csw = 0.32 fF Cg = 2.02 fF 14/02/2009 VLSI Design

Source/drain resistance Scaled down devices  higher source/drain resistance: In sub- processes silicidation is used to reduce the source, drain and gate parasitic resistance 0.24 mm process R (P+) = 4 W/sq R (N-) = 4 W/sq 14/02/2009 VLSI Design

New Interconnect Materials Aluminium  Copper Lower resistivity Higher immunity to Electromigration SiO2  Low-k dielectrics 14/02/2009 VLSI Design

--Take up one Idea. Make that Idea your life. Think of it. Dream of it --Take up one Idea. Make that Idea your life. Think of it .Dream of it. Live on that Idea .Let the brain, muscles, nerves and every part of your body, be full of that idea and just leave every other idea alone. This is the way to success……. 14/02/2009 VLSI Design