Not a BIS expert, not even working on BIS but I’m going to try to present it as completely as possible

Plan Safe Machine Parameters - Tester SMP Tester Hardware Short Historic Version 1 - LabVIEW tester Version 2 - Generic test and virtual SMPC Version 3 - Need for speed Safe Machine Parameters - Tester SMP Tester Hardware Short Historic Version 1 - LabVIEW tester Version 2 - Generic test and virtual SMPC Version 3 - Need for speed CERN, the LHC and Machine Protection

SMP reminder Frames Flags CERN, the LHC and Machine Protection I. SMP Tester Hardware

Notions (1): Frames and flags Frames transmission Electronic board 32 bits 1 0 1 0 1 1 0 1 0 0 1 ME MD ≈ 100us Manchester Encoder Manchester Decoder Flags transmission Electronic board 0 or 1 1 bit < 1us CERN, the LHC and Machine Protection I. SMP Tester Hardware

Notions (2): FPGA memories 32 bits Registers History buffer (HB) 128 bits 1024 records UTC Time MONITOR CONTROL Event Seconds Microseconds Status Visibility Type Sub-type Details 32-bits 20-bits 12-bits 16-bits 2-bits 6-bits 8-bits DW0 DW1 DW2 DW3 CERN, the LHC and Machine Protection I. SMP Tester Hardware

HW tester simulation SMPC CIBFU CIBFC BCTs BEMs CISC CIBU LHC BIS GMT BPF CISC CIBU LHC BIS GMT CISV BETS DCCT En, Int CISR A CISR B CISGL A CISGL B CISA SMPC Electrical-differential RS485 Current loops Optical Manchester encoded frames Flags CIBFU CIBFC SPS Ext BIS BPF SBF 5 CISTR 2 CISTCL 1 CISTA CERN, the LHC and Machine Protection I. SMP Tester Hardware

HW tester connections C I S C CERN, the LHC and Machine Protection I. SMP Tester Hardware

Plan Safe Machine Parameters - Tester SMP Tester Hardware Short Historic Version 1 - LabVIEW tester Version 2 - Generic test and virtual SMPC Version 3 - Need for speed CERN, the LHC and Machine Protection

Historic Developments Version 1: until August 2011 Version 2: from May to October 2011 Version 3: from November 2011 (to May 2012?) CERN, the LHC and Machine Protection II. Short historic

Plan Safe Machine Parameters - Tester SMP Tester Hardware Short Historic Version 1 - LabVIEW tester Version 2 - Generic test and virtual SMPC Version 3 - Need for speed CERN, the LHC and Machine Protection

Version 1: Layers overview Excel Command Results LabVIEW LabExcel SMPC Tester FESA vi FESA FESA dll Ethernet communication PowerPC (FESA drivers) VME boards Electronic cards CERN, the LHC and Machine Protection III. Version 1 - LabVIEW tester

New test => New LabVIEW code ! Version 1: Test steps Main limitation: New test => New LabVIEW code ! FESA vi PowerPC (FESA drivers) Electronic cards Ethernet communication FESA dll SMPC Tester LabExcel Command Results Command Results LabExcel SMPC Tester FESA vi VME bus FESA dll Ethernet communication PowerPC (FESA drivers) Electronic cards CERN, the LHC and Machine Protection III. Version 1 - LabVIEW tester

Plan Safe Machine Parameters - Tester SMP Tester Hardware Short Historic Version 1 - LabVIEW tester Version 2 - Generic test and virtual SMPC Version 3 - Need for speed Safe Machine Parameters - Tester SMP Tester Hardware Short Historic Version 1 - LabVIEW tester Version 2 - Generic test and virtual SMPC Version 3 - Need for speed CERN, the LHC and Machine Protection

Version 2: Brain storming Goal 1: Add/modify tests out of LabVIEW => Tests defined in Excel A test  Operations to perform How many possible operations? => 7 Set Wait Get Goal 2: Separate the test operations of the test validation SMP controller Test program Expected behavior calculation Generate inputs from Excel command = Test success Yes Simulates at every time (ms granularity): The output signals The internal memory (only registers) => Birth of the Virtual SMP controller CERN, the LHC and Machine Protection IV. Version 2 - Generic test and virtual SMPC

Version 2: Code overview SMP controller Test program Expected behavior calculation Generate inputs from Excel command = Test success Yes CERN, the LHC and Machine Protection IV. Version 2 - Generic test and virtual SMPC

Version 2: User’s interface Ctrl + Click Shift + Click Ctrl + Shift + Click CERN, the LHC and Machine Protection IV. Version 2 - Generic test and virtual SMPC

Version 2: Limitations - Maintain the Virtual SMPC code (not really an issue) - Implementation of the History Buffer behavior - Very slow: 1Hz(FESA subscription / FESA refresh) total time 120 tests: SMPC = 6h 40m VSMPC = 1h 20m 1. Formal Methods ? CISR model CISGL too complex CISR input headers BPF Energy priority 2. Accelerate FESA refresh at 10Hz? => PowerPC overloaded… CERN, the LHC and Machine Protection IV. Version 2 - Generic test and virtual SMPC

Plan Safe Machine Parameters - Tester SMP Tester Hardware Short Historic Version 1 - LabVIEW tester Version 2 - Generic test and virtual SMPC Version 3 - Need for speed Safe Machine Parameters - Tester SMP Tester Hardware Short Historic Version 1 - LabVIEW tester Version 2 - Generic test and virtual SMPC Version 3 - Need for speed CERN, the LHC and Machine Protection

Version 3: Requirement The virtual SMP has to be removed (cannot be faster) => Expected values for registers and HB have to be in Excel FESA must be replaced => Nodal? Too basic, old, no support… => c code implementation ! Excel LabVIEW VME boards FESA vi PowerPC (FESA drivers) Electronic cards Ethernet communication FESA dll SMPC Tester LabExcel Command Results Developped under Visual Studio Socket implementation (with Jean-Christophe’s help) C dll Server client FESA Ethernet (TCP protocol) c function to access boards memories (provided by Ben) .h libraries search (J-C’s help) PowerPC (c server) CERN, the LHC and Machine Protection V. Version 3 - Need for speed

Version 3: Timing Performances Test protocol: - Read from LabVIEW a bloc of memory = (32*Nb registers read) bits => One 32-bits register read in 2 microseconds => 1ms offset due to the socket connection CERN, the LHC and Machine Protection V. Version 3 - Need for speed

Version 3: Timing management Each VME-crate has a server running → time synchronization needed How to implement the Wait function? Use of c functions (rdtsc, usleep, nanosleep, …)? They are system dependant Use of the UTC time in the FPGA registers. 2 registers in each board: - UTC_SECOND : set by the tester through the socket UTC_MICROSECOND : set to 0 each pulse on pps boards input (lemo cable, few nanoseconds precision). Timing error t [us] 2us Read reg 1000 Wait (1000us) 1000us Still subject to system interruptions! => Timing error generation CERN, the LHC and Machine Protection V. Version 3 - Need for speed

Version 3: Tests operations Tester 2 (7 op): -Send frame -Send flag -Write register -Read register -Read signal -Read HB -Wait Tester 3 (9 op): -Set frame -Set flag -Enable generators -Write register -Read register -HB Start read -HB Get records -Wait -For: repeats a set of operations (reduce socket data transfer) Get info back: Compare with expected (Excel) HB interpretation* Generate timing error Need for synchronization Only last events *HB interpretation: Presence of record Record data expected (energy value, control status…) Time spent between specific records (CISR validity input) CERN, the LHC and Machine Protection V. Version 3 - Need for speed

Version 3: Example (CISR headers) General Goal: Test the channel 1 energy input on CISRA of the LHC SMPC HDR Energy CRC 8 bits = 2 hexa 32 bits 1 input frame = Valid header: x92 Specific goals (from specification): Test all 256 headers and check the Valid flag (1 bit in a register) is true only for x92 Check the validity time is 7 times the energy frame period Test steps: Send each header once, period T=1000us between each frame Check the valid flag is false for all except x92 (check done tc=200us after the frame sending) Check the flag stays true 7*T=7000us x93 x94 … xFF x00 … x91 x92 T 7*T FALSE t [us] tc FALSE TRUE Valid Flag CERN, the LHC and Machine Protection V. Version 3 - Need for speed

Version 3: Example (CISR headers) x93 x94 … xFF x00 … x91 x92 FALSE TRUE T t [us] 7*T Valid Flag tc Time spent: 5600 + 200 + 1000*255 + 7000 = 267 800 us 12 to 13 min VS 0.3 seconds CERN, the LHC and Machine Protection V. Version 3 - Need for speed

Version 3: Limitations None ? CERN, the LHC and Machine Protection V. Version 3 - Need for speed

END ! Version 3: ToDo Low level implementation (c): History Buffer interpretation Remove text file between LabVIEW and the c dll Tests definition (Excel): Re-define all tests (4/120 done). For both SPS and LHC Add the CISC tests High level language (LabVIEW, LabWindowsCVI, Java…): Design the tests viewer Develop a test builder CERN, the LHC and Machine Protection V. Version 3 - Need for speed