ECE 4110– 5110 Digital System Design

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Presentation transcript:

ECE 4110– 5110 Digital System Design FPGA notes Agenda CPLDs FPGAs Announcements n/a Page 1

Figure 9-38: A 4x3 PLA with six product terms Lecture #3 Page 2

PLD split Page 3

Lecture #3 Page 4

Figure 9-39: Architecture of Xilinx 9500-family CPLDs Page 5

Lecture #3 Page 6

Figure 9-41: XC9500 product-term allocator and macrocell. Page 7

Figure 9-42: XC9500 I/O block Page 8

Figure 9-43: XC95108 switch-matrix requirements.. Page 9

Figure 9-44: General FPGA chip architecture. Page 10

Lecture #3 Page 11

Figure 9-45: XC4000 configurable logic block. Page 12

Figure 9-46: XC4000 I/O block. Page 13

Figure 9-47: XC4000 general interconnect structure. Page 14

Figure 9-48: XC4000 CLB and wire connection details. Page 15

Figure 9-49: XC4000 programmable connections: (a) programmable switch matrix (PSM); (b) programmable switch element (PSE); (c) a few possible connections. Page 16