V. Suntharalingam 5 February 2008 APS-2 Test Status V. Suntharalingam 5 February 2008 Please note with the scope traces here that we can’t easily subtract the input and output waveforms because I didn’t make sure that the offsets were all set to be the same or some known (recorded) value. These curves are intended to be quallitative. When I do it again, I’ll keep track of that so that a better quantitative assessment can be done.

APS-2 Test Status Single Pixel Addressing within Array Next: Observe photoresponse with oscilloscope Evaluate Output signal swing (dark to saturated) Determine if ICMPIX needs further adjustment Determine if capacitor is present Test conditions -- New Chip Chip: 21A w3 r2c3 no quartz support Covered with black cloth in dark room, but stray light is a problem! Test points for bias supplies verified at board (confirms no droop) VRST1 = VRST2 = VSCP =1.5V VDDA = VDDD = VDD_ESD = 3.3V VSIG_out/10kohm to -4V VPDBIAS = 5V for scope ICMPIX = 5uA, ICMNCOL = 10uA, ICMP = -20uA Next: Light-tighten package Square wave input on VRST1 (monitor output rise/fall time) Gain/bandwidth curve from single pixel Cd-109 exposure with this chip Other items discussed in meeting (see Mark’s notes)

Dark/Light Response Chip w3 r2c3 Pointing Down - Reflected Room Light Chip obscured by package here PD=5V PD=10V 12-bit counts range from -2048 to +2048 ADC input range here +/- 1V “Light” image has higher ADU units

Spatial Variation from Averaged Frame (10f) Comments:  +/- 200mV input is broader in ADU  Mean signal higher for PD =10V - Similar spatial distribution for PD=5 or 10V

Temporal Noise Measured over 10-Frames All 256 x 256 pixels PD=5V PD=10V While the average pixel has similar noise there is a broader distribution for PD=10V. This makes sense from the greater volume of depleted silicon. Could noise variation across the array (the spread here) obscure the Xray peak? e.g. 6000e- * 8µV/e- * 1ADU/488µV = 98 ADU for +/-1 V ADC input capture range

Temporal Noise Measured over 10-Frames Sub Array +/- 1V input range +/- 200mV input range

VRST1 Or DC 1.5V

Single Pixel Test Pixel R95 C159 - Short Integration Time Pre-capture 0.4ms Reset 1.6ms Integrate Vout RSTG1 Short integration time: very little dark current accumulated to increase signal out (Vout)

Single Pixel Test Pixel R95 C159 – Long Integration Time Pre-capture 1s Reset 4s Integrate Vout RSTG1 Long integration time: see dark current accumulation and signal saturation (Vout swing ~1V) This instance saturates in ~ 1.75sec. Stray light can make this vary

Median time to saturate from array (~2 Median time to saturate from array (~2.5sec) is similar to single pixel measurement (1.75sec), given stray light concerns

Exercise Pixel Speed Reset: 8µs Integrate:32µs Reset: 20µs Reset: 0.4ms Integrate: 1.6ms Reset: 1ms Integrate: 4ms Reset: 1.6s Integrate: 0.4s

RSTG1 Is ON; RSTG2 Is Pulsed (Active Low) VRST = 1.5V DC Pre-capture RSTG2 OFF ON Vout RSTG1 RSTG2 VRST1 VRST2 = 1.5V RSTG1 ON RSTG1 conducting to pass through DC level from VRST1 Output held to DC level by RSTG1 - Pixel does not integrate

RSTG1 Is ON; RSTG2 Is OFF (Active Low) VRST1 = 1kHz Input Sine Wave RSTG2 OFF Vout RSTG1 RSTG2 VRST1 VRST2 = 1.5V RSTG1 ON RSTG1 conducting to pass through sine wave RSTG2 not conducting Gain here 0.98/1.16 = 0.848 for 1kHz input; need to find Gain=1 point

RSTG1 Is ON; RSTG2 Is Pulsed (Active Low) VRST1 = 1kHz Input Sine Wave OFF ON RSTG2 OFF Vout RSTG1 RSTG2 VRST1 RSTG1 conducting to pass through sine wave RSTG2 pulsed When ON, pixel is reset to VRST2 = 1.5V When OFF, pixel passes through input sine wave from VRST1 CDS-induced subtraction relative to reset level is seen (see next slide) VRST2 = 1.5V

RSTG1 Is ON; RSTG2 Is Pulsed (Active Low) VRST1 = 100MHz Input Sine Wave OFF ON OFF ON Similar conditions as previous slide CDS-induced subtraction relative to reset level is seen (white arrow) VRST2 = 1.5V Vout RSTG1 RSTG2 VRST1