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FEATURES OF GOOD MEMORY ABILITY TO RETAIN STORED CHARGE FOR LONG PERIODS WITH ZEROAPPLIED OR REFRESHED POWER. HIGH SPEED OF DATA WRITES. LOW POWER CONSUMPTION. LARGE NO: OF WRITE CYCLES. Actually none of the present memory technologies combine these features. www.ppttopics.com

RECENT ADVANCED MEMORY TECHNOLOGIES MRAM FRAM OUM www.ppttopics.com

MRAM USES MAGNETIC TUNNEL JUNCTION AND TRANSISTOR. ELECTRIC CURRENT SWITCHES THE MAGNETIC POLARITY. THAT SWITCHING CHANGES IS SENSED AS A RESISITANCE CHANGE. www.ppttopics.com

FRAM USES A CRYSTAL UNIT CELL IT IS MADE OF PERVOSKITE - PZT (i.e. LEAD ZIRCONATE TITANATE) DATA IS STORED BY APPLYING A VERY LOW VOLTAGE. ELECTRIC FIELD MOVES THE CENTRAL ATOM BY CRYSTAL ORIENTATION OF UNIT CELL. IT RESULTS IN POLARIZATION OF INTERNAL DIPOLES. www.ppttopics.com

OUM OVONIC UNIFIED MEMORY www.ppttopics.com

HISTORY R.G.NEALE , D.L.NELSON , GORDEN.E.MOORE ORIGINALLY REPORTED PHASE CHANGE MEMORY IN 1970. IT WAS BASED ON CHALCOGENIDE MATERIALS. THE IMPROVEMENTS IN PHASE CHANGE MEMORY LEAD TO OUM TECHNOLOGY. THE PRESENT PHASE CHANGE MEMORY IS CALLED OUM. www.ppttopics.com

OUM www.ppttopics.com

OUM OUM IS A NON VOLATILE MEMORY TECHNOLOGY WITH: HIGH SPEED LOW POWER REDUCED COST HIGH ENDURANCE MERGED MEMORY / SIMPLIFIED LOGIC EMBEDDED CMOS APPLICATIONS www.ppttopics.com

Material Science and Device Physics Technology Material Science and Device Physics www.ppttopics.com

ARCHITECTURE www.ppttopics.com

MEMORY STRUCTURE www.ppttopics.com

MEMORY STRUCTURE TOP ELECTRODE CHALCOGENIDE LAYERS RESISTIVE HEATER THERMAL INSULATOR www.ppttopics.com

ABOUT CHALCOGENIDE ALLOY CHALCOGENIDE ALSO CALLED PHASE CHANGE ALLOYS ITS A PART OF OUM’S STRUCTURE ITS A TERNARY SYSTEM IT CONSISTS OF GALLIUM , ANTIMONY & TELLURIUM CHEMICALLY CALLED Ge2Sb2Te5 PRODUCED BY MELTING & SUBSEQUENT MILLING OF RAW MATERIAL POWDERS ARE PROCESSED BY HOT ISOTACTIC PRESSING www.ppttopics.com

AMORPHOUS PHASE CRYSTALLINE PHASE www.ppttopics.com

COMPARISON AMORPHOUS PHASES CRYSTALLINE PHASES SHORT RANGE ATOMIC ORDER LOW FREE ELECTRON DENSITY HIGH ACTIVATION ENERGY HIGH RESISTIVITY LONG RANGE ATOMIC ORDER HIGH FREE ELECTRON DENSITY LOW ACTIVATION ENERGY LOW RESISTIVITY www.ppttopics.com

WORKING www.ppttopics.com

PROGRAMMING The OUM cell is programmed by application of a current pulse at a voltage above the switching threshold. The programming pulse drives the memory cell into a high or low resistance state, depending on magnitude of the pulse voltage. Information stored in the cell is read out by measurement of the cell’s resistance. OUM devices are programmed by electrically altering the structure (amorphous or crystalline) of the small volume of chalcogenide alloy. www.ppttopics.com

OPERATION Ovonic Unified Memory is a new semiconductor memory technology, originally invented by Energy Conversion Devices, Inc. (ECD), and now licensed exclusively to Ovonyx , Inc. OUM uses a reversible structural phase-change from the amorphous phase to a crystalline phase in a thin-film chalcogenide alloy material as the data storage mechanism. The small volume of active media in each memory cell acts as a fast programmable resistor, switching between high and low resistance with >40X dynamic range. www.ppttopics.com

Phase-change technology is well established, and is the basis for the current CD RW, PD, DVD-RAM and DVD+RW optical disk memory products. OUM offers advantages in cost and performance over conventional DRAM and Flash memories, and it is compatible with merged memory/logic. OUM technology uses a conventional CMOS process with the addition of a few additional layers to form the thin-film memory element. OUM products are now being commercialized through a number of licensing agreements and joint development programs with Ovonyx www.ppttopics.com

BASIC DEVICE OPERATION DURING AMORPHIZING RESET PULSE, THE TEMP OF MATERIAL EXCEEDS MELTING POINT ELIMINATES THE POLY CRYSTALLINE ORDER OF MATERIAL CRYSTALIZING SET PULSE IS OF LOWER AMPLITUDE SUFFICIENT DURATION TO MAINTAIN THE DEVICE TEMP IN RAPID CRYSTALLIZATION RANGE www.ppttopics.com

READING & WRITING DATA TO WRITE DATA TO READ DATA CHALCOGENIDE IS HEATED ABOVE ITZ MELTING POINT TO RESET STATE [HIGH RESISTANCE] HEATED BELOW ITZ MELTING POINT FOR 50nS TO SET STATE [LOW RESISTANCE] READING IS DONE BY SIMPLY MEASURING THE RESISTANCE CHANGE. HIGH RESISTANCE = SET STATE LOW RESISTANCE = RESET STATE www.ppttopics.com

V-I CHARACTERISTICS AT LOW VOLTAGES THE DEVICE EITHER LOW RESISTANC ~ 1K OR HIGH RESISTANCE >100K THIS IS THE READ OPERATION REGION TO PROGRAM THE DEVICE , A PULSE OF SUFFICICIENT VOLTAGE IS APPLIED SWITCHES TO DYNAMIC ON STATE FOR RESET IT REQUIRES A VOLTAGE GREATER THAN V th V th IS DEVICE PARAMETER ie, .5 v to .9 v THE RECIPROCAL OF V-I CURVE IN DYNAMIC ON STATE IS THE SERIES DEVICE RESISITANCE www.ppttopics.com

R-I CHARACTERISTICS DEVICES CAN BE SAFELY RESET ABOVE SATURATION POINT AS AMPLITUDE INCREASES,MOVING FROM LEFT TO RIGHT THE DEVICE CONTINUES TO REMAIN IN SET STATE INCREASE IN AMPLITUDE BEGINS TO RESET THE DEVICE WITH FURTHER INCREASE RESETTING THE DEVICE TO STANDARD AMORPHOUS STATE PROGRAMMED RESISTANCE REDUCED AS CRYSTALLIZATION OF THE MATERIAL IS ACHIEVED FURTHER INCREASE IN PROGRAMMING CURRENT FURTHER CRYSTALLIZES THE MATERIAL ,WHICH DROPS THE RESISTANCE TO MINIMUM VALUE DEVICES CAN BE SAFELY RESET ABOVE SATURATION POINT www.ppttopics.com

TECHNOLOGY & PERFOMANCE DEVICE RESISTANCE Vs WRITE PULSE WIDTH RESET RESISTANCE SATURATES WHEN THE PULSE WIDTH IS LONG ENOUGH TO ACHIEVE MELTING OF PHASE CHANGE MATERIAL THE SET PULSE CRYSTALLIZES THE BIT IN 50ns WITH A RESET / SET REISITANCE RATIO OF GREATER THAN 100 www.ppttopics.com

ADVANTAGES www.ppttopics.com

NEAR IDEAL MEMORY QUALITY HIGHLY SCALABLE LOGIC PROCESS COMPATABLE COST / BIT REDUCTION NEAR IDEAL MEMORY QUALITY HIGHLY SCALABLE LOGIC PROCESS COMPATABLE RADIATION IMMUNITY 3D NATURE www.ppttopics.com

COST / BIT REDUCTION? SMALL ACTIVE STORAGE MEDIUM SMALL CELL SIZE SIMPLE MANUFACURING PROCESS SIMPLE PLANAR DEVICE STRUCTURE LOW VOLTAGE – SINGLE SUPPLY REDUCED ASSEMBLY & TEST COSTS www.ppttopics.com

NEAR IDEAL MEMORY QUALITY? NON VOLATILE HIGH ENDURANCE ->1013 CYCLES LOW DATA RETENTION ->10 YEARS STATIC – NO REFRESH OVERHEAD PENALTY RANDOM ACCESSIBLE – READ & WRITE DIRECT OVERWRITE CAPABILITY LARGE DYNAMIC RANGE FOR DATA (>40X) GOOD ARRAY EFFICIENCY NO CHARGE LOSS FAILURE MECHANISMS HIGH SWITCHING SPEED NON DESTRUCTIVE READ www.ppttopics.com

HIGHLY SCALABLE? PERFORMANCE IMPROVES WITH SCALING ONLY LITHOGRAPHY LIMITED LOW VOLTAGE OPERATION MUTI STATE DEMONSTRATED 3D MULTI LAYER POTENTIAL WITH THIN FILMS HIGHER DENSITY EASE OF INTEGRATION www.ppttopics.com

LOGIC PROCESS COMPACTABLE? LATE LOW TEMP PROCESSING ADDS 2 TO 4 MASK STEPS TO CONVENTIONAL CMOS LOGIC PROCESS WITH LOW TOPOGRAPHY LOW VOLTAGE OPERATION ENABLES ECONOMIC MERGED MEMORY / LOGIC ENABLES REALISTUC SYSTEM ON A CHIP (SOC) www.ppttopics.com

RADIATION IMMUNITY? AS THE BITS ARE NOT STORED IN FORM OF CHARGE OR LINKS BUT IN FORM OF TWO DEFINITE PHASES CRYSTALLINE AMORPHOUS HENCE OUM CAN BE SAFELY EMPLOYED IN ALL MEDICAL & SPACE APPLICATION www.ppttopics.com

3D NATURE ? ANOTHER IMPORTANT CHARACTERISTIC OF OUM IS 3D NATURE.OUM CAN BE GROWN IN 3 DIMENSION THERE BY OFFERING EVEN HIGH DENSITY USING A SMALL AREA www.ppttopics.com

TECHNOLOGY CAPABILITIES DIRECT WRITE CAPABILITY (no erase before write) AS WELL AS BYTE FUNCTION (no block flash erase) MAKES IT RAM LIKE FOR FLASH CHANGING A BYTE INVOVLES SAVING THE CURRENT DATA ,ERASING A WHOLE BLOCK (>100mSec) & WRITING BACK OLD DATA + NEW DATA (total ~ 1Sec) FOR OUM CHANGING A BYTE INVOLVES THE NEW DATA (total < 100nSec can be less than 50nSec with new alloy) DEMONSTRATED ENDURANCE OF 1013 CYCLES WITH READ CURRENT > 10 micro A , READ SPEED IS EXPECTED TO BE COMPARABLE TO NOR & DRAM THE DEVICE HAS EXCELLENT LIFE AS FAILURE OCCURRENCE IS NEGLIGIBLE www.ppttopics.com

OUM:A MEMORY 4 EVERYBODY FOR EMBEDDED WITH THE SMALLEST AMOUNT OF PROCESS CHANGE ONE CAN GET A HIGH CYCLE EEPROM EQUIVALENT AT LOWER COST BY USING THE SAME PROCESS BUT CHANGING THE ALLOY ONE CAN GET A HIGH TEMPARATURE MEMORY SUITABLE FOR THE MOST DEMANDING AUTOMOTIVE APPLICATION FOR DEDICATED HIGH DENSITY MEMORY ONE CAN GET A MEMORY CELL THAT IS SMALLER THAN DRAM & HAS MULTI LEVEL CELL CAPABILITY USING HIGH PERFORMANCE ALLOYS PROGRAMMING SPEED SIMILAR TO DRAM ARE AVAILABLE USING SPECIAL SWITCHED SELECTORS ONE CAN GET MULTI LAYER MEMORY THAN CAN RIVAL NAND MEMORY IN COST www.ppttopics.com

RISK FACTORS OF OUM ? RESET CURRENT < MIN SWITCH CURRENT STANDARD CMOS PROCESS INTEGRATION ALLOY OPTIMIZATION FOR HIGH TEMP OPERATION & SPEEED ENDURANCE TESTING TO 1014 DRAM DEFECT DENSITY & FAILURE MECHANISMS www.ppttopics.com

TECHNOLOGY CHALLENGES REDUCTION OF PROGRAMMING CURRENT FOR LOWER VOLTAGE & LOWER POWER OPERATION INCREASED SET / RESET RESISTANCE DECREASED READ CURRENT / SET CURRENT MANAGEMENT OF PROXIMITY HEATING WITH DECLINING CELL SPACE – DISTURB RISK www.ppttopics.com

INITIAL TARGET MARKETS FLASH – PIN COMPATIBLE FPLD , FPLA – PIN COMPATIBLE DRAM – PIN COMPATIBLE EMBEDDED MACROS SOC MACROS SRAM – CACHE , BATTERY ,FAST ROM – PIN COMPATIBLE ENCRYPTION NEURAL COMPUTING DIGITAL SIGNAL PROCESSING POWER SWITCHING SMART CARDS SERIAL EEPROM www.ppttopics.com

CONCLUSION NEAR IDEAL MEMORY QUALITIES BROADENS S/M APPLICATIONS EMBEDDED CMOS INTEGRATION SYSTEM-ON-CHIP (SOC), other products HIGHLY SCALABLE RISK FACTORS ARE IDENTIFIED TIME TO PRODUCTIZE www.ppttopics.com

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