Implementing Instructions

Machine Cycle Fetch Decode Execute

Architeture High level architecture

Detailed View Data/Address Paths Not shown: Control signals

Special Purpose Registers PC : Current Instruction Address IR : Current Instruction MAR : Address to get/store MBR : Data to get/store

RTN RTN : Register Transfer Notation [r1]  [r3] + [r2] r1 gets set to sum of values in r2 and r3 [PC]  [PC] + 4 PC gets set to sum of PC and 4 [r1]  [[MAR]] r1 gets set to the value in the memory location stored in MAR [ALU:P]  [r1] The P input of ALU gets the value stored in r1

Fetch Step 1 Copy PC to MAR [MAR]  [PC] Step to next instruction [PC]  [PC] + 4

Fetch Step 1 Copy PC to MAR [MAR]  [PC] Step to next instruction [PC]  [PC] + 4

Fetch Step 2 Retrieve Intruction from memory [MBR]  [[MAR]] 0x00001000 Retrieve Intruction from memory [MBR]  [[MAR]]

Fetch Step 2 Retrieve Intruction from memory [MBR]  [[MAR]] 0x00001000 Retrieve Intruction from memory [MBR]  [[MAR]] 0xE59F100C

Fetch Step 3 Put instruction in IR [IR]  [MBR] 0xE59F100C

Fetch Step 3 Put instruction in IR [IR]  [MBR] 0xE59F100C 0xE59F100C

Fetch Summary [MAR]  [PC] [PC]  [PC] + 4 [MBR]  [[MAR]] [IR]  [MBR]

Decode Control unit reads opcode, sets control lines 0xE59F100C

LDR Instruction represents: LDR r1, x 0xE59F100C

Execute LDR Step 1 Copy Operand part of IR to MAR [MAR]  [IR(Operands)] OR [MAR]  [IR(Address)] 0xE59F100C

Selecting MBR Source Any time two lines join, need a multiplexer:

Execute LDR Step 1 Copy Operand part of IR to MAR 0x100C Copy Operand part of IR to MAR [MAR]  [IR(Operands)] OR [MAR]  [IR(Address)] 0xE59F100C

Execute LDR Step 2 0x100C Get date from memory [MBR]  [[MAR]]

Execute LDR Step 2 0x100C Get date from memory [MBR]  [[MAR]] 5

Execute LDR Step 3 Store to register [r1]  [MBR] 5

Execute LDR Step 3 Store to register [r1]  [MBR] 5 5

LDR Summary [MAR]  [IR(Operands)] [MBR]  [[MAR]] [r1]  [MBR]

ADD Instruction represents: ADD r3, r1, r2 0xE0813002

ADD Step 1 Store to register [ALU:P]  [r1] [ALU:Q]  [r2] 4 3

ADD Step 1 Store to register [ALU:P]  [r1] [ALU:Q]  [r2] 4 3 4 3

ADD Step 2 Write result to register [r3]  [ALU:P] + [ALU:Q] OR [r3]  [r1] + [r2] 4 3

ADD Step 2 Write result to register [r3]  [ALU:P] + [ALU:Q] OR [r3]  [r1] + [r2] 7 4 3

ADD Summary [ALU:P]  [r1] [ALU:Q]  [r2] [r3]  [ALU:P] + [ALU:Q] OR [r3]  [r1] + [r2]

Immediates Instruction represents: MOV r2, #4 0xE3812004

Move Immediate Step 1 Move operand bits to r2 [r2]  [IR(Operands)] 0xE3820004

Move Immediate Step 1 Move operand bits to r2 [r2]  [IR(Operands)] 0xE3820004 0x0004

Add Immediate Instruction represents: ADD r2, r1, #4 0xE5210004 3

Add Immediate Step 1 Move immediate to Q Move r1 to P [ALU:Q]  [IR(Operands)] [ALU:P]  [r1] 0xE5210004 3

Add Immediate Step 1 Move immediate to Q Move r1 to P [ALU:Q]  [IR(Operands)] [ALU:P]  [r1] 0xE5210004 3 3 0x0004

Add Immediate Step 2 Store result to r3 [r2]  [ALU:P] + [ALU:Q] 3 0x0004

Add Immediate Step 2 Store result to r3 [r2]  [ALU:P] + [ALU:Q] 7 3 0x0004

Add Immediate Summary [ALU:Q]  [IR(Operands)] [ALU:P]  [r1] [r2]  [ALU:P] + [ALU:Q]

Branches Instruction represents BEQ foo Where foo is at 2024 0xEA612024

Branches EQ means Z(ero) flag is set If Z, set PC to 2024 0xEA612024

Branches Possibility 1 If Z, set PC to 2024 RTN: If [Z] = 1 THEN [PC]  [IR(Operands)] 0xEA612024 1010

Branches Possibility 1 If Z, set PC to 2024 RTN: If [Z] = 1 THEN [PC]  [IR(Operands)] 0x2024 0xEA612024 1010

Branches Possibility 2 If Z, set PC to 2024 RTN: If [Z] = 1 THEN [PC]  [IR(Operands)] 0xEA612024 0010