Space vs. Speed: Binary Adders

Binary Adders VHDL Adder Carry Lookahead Adder

4-Bit Adder C 1 1 1 0 A 0 1 0 1 B 0 1 1 1 S 1 1 0 0

Adder in VHDL entity adder is port ( a: in STD_LOGIC_VECTOR (3 downto 0); b: in STD_LOGIC_VECTOR (3 downto 0); sum: out STD_LOGIC_VECTOR (3 downto 0); carry: out STD_LOGIC ); end adder;  

std_logic_arith.vhd

Ci AiBi 00 01 11 10 1 1 1 1 1 Ci+1 Ci+1 = Ai & Bi # Ci & Bi # Ci & Ai

std_logic_unsigned.vhd

adder.vhd

Binary Multiplier 2 bit by 2 bit Half Adders are Sufficient Since there is no Carry-in in addition to the two inputs to sum

Binary Multiplier 4 bit by 3 bit 4 bit by 3 bit yields 7 bit result

Binary Adders VHLD Adder Carry Lookahead Adder

Carry Lookahead Adder C2 = G1 + P1(G0 + P0C0) = G1 + P1G0 + P1P0C0 C3 = G2 + P2(G1 + P1 (G0 + P0C0)) = G2 + P2(G1 + P1 G0 + P0C0) = G2 + P2G1 + P2P1G0 + P2PlP0C0   G0-3 = G3 + P3G2 + P3P2G1 + P3P2PlG0 P0-3 = P3P2PlP0

Ripple Carry Adder (4-bit)

Typically, longest delay path through n-bit ripple carry adder is 2n + 2 Tends to be one of the largest delays in a typical computer design Counts as 2 gate delays 2 2 4 1 3 4 1

4 4 2 6 5 6 4

6 4 6 4 2 8 7 8 6

8 6 4 8 6 4 2 10 9 10 8

8 10 6 4 10 8 6 4 10 Gate Delays 16-bit Adder -- 34 Gate Delays 64-bit Adder -- 130 Gate Delays

Carry Lookahead Adder Uses Propogate and Generate signals to “lookahead” for incoming carry signals More complicated hardware configuration Substantial decrease in gate delays

Ripple Carry PFA: Partial Full Adders Carry Lookahead

Propagate. P = A xor B. If P = ‘1’ then the carry is “propagated” Propagate P = A xor B If P = ‘1’ then the carry is “propagated” through. If P = ‘0’ then the carry is not “propagated” through. Generate G = A and B If G = ‘1’ a carry is “generated” regardless of the carry bit.

For final carry determination, the Propagate signal is ANDed with the Carry Out and the Generate signal is ORed to the resulting signal. G P Cin Cout Cin A B 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Cout S 0 0 0 1 1 0 1 1 P G

Cin A B 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Cout S 0 0 0 1 1 0 1 1 P G Always Generate a Carry for A = 1, B =1 Cin A B 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Cout S 0 0 0 1 1 0 1 1 P G Propagate the Carry in

Cout

2 4 1 2 4 3 Cout

2 4 PFA For Bit # 1 1 2 4 1 3 4 2 2 3 2 3 1 4 2 1 2 Cout 3 2 3 1 4 2

Bit #2 Bit #1 2 2 4 6 1 1 4 Bit #4 Bit #3 2 2 6 6 1 4 4

Significant Delay Reduction 4 - bit Ripple: 10 Delays CLA: 6 Delays 1 CLA level: 1*4 + 2 = 6 16 - bit Ripple: 34 Delays CLA: 10 Delays 2 CLA levels: 2*4 + 2 = 10 64 - bit Ripple: 130 Delays CLA: 14 Delays 3 CLA levels: 3*4 + 2 = 14 But at the expense of a significant increase in the number of gates used by the circuit