INFIERI FermiLab Meeting October 21, 2016

What are the drivers of change?

Precipitating Events for Change

Expiring Economics AMD 2014 3D-ASIP

Cost Trend Reversal AMD 2014 3D-ASIP

The Apples & Oranges of SOC AMD 2014 3D-ASIP

Internet Of Things ImpactLab.net Societyofrobots.com 7

More Than Moore GEORGIA TECH PRC

More than Moore

The Fabrication Road to More Than Moore Memories, CMOS, Photonics, III-V, Novel Materials, Microfluidics, MEMS, etc. Build novel structures BEOL Start with FEOL CMOS wafer

Integration Paths: Additive Silicon and 2.5/3D BEoL++ BEoL+ Si 3-D TSVs CMOS CMOS Figure 1: Non-digital devices built directly on CMOS (left), or built separately and joined through 3-D TSVs

8 Layer Logic Stack

16 Layer Mechanical Device Stack

The Semiconductor Revolution Samsung 16Gb NAND flash (2Gx8 chips), Wide Bus DRAM, VNAND 560μ Hynix HBM DRAM Intel CPU + memory Sony CMOS Sensor Xilinx 4 die 65nm interposer AMD Radon R9 IBM RF Silicon Circuit Board / TSV Logic & Analog Toshiba 3D NAND

Si Interposer-based Ceramic Package HPC Processor Modules Silicon Interposer DiRAM4 ASIC Support Chips DiRAM4 Ceramic Pkg Substrate Si Interposer-based Ceramic Package e.g. DiRAM4 plus Custom Processor 50 µ - 100 µ pitch Copper Pillar Die-to-Interposer-to-Die Interconnect ~ 10000 Connections – Mostly die-to-die inside package ~250 µ pitch C4 Bump Interposer-to-Ceramic Package Substrate Interconnect ~ 2000 Connections – Lots of replicated power connections 1 mm pitch Solder Bump Package Substrate-to-Customer PCB Interconnect Several Hundred of Connections Presented here is a typical 2.5D implementation using Tezzaron’s DiRAM4 memories for a processor module. This technique which utilizes split-fabrication as well as 2.5 and 3D integration creates a processor element that is superior to any 2D device available today or that is likely to ever be available in CMOS.

And Full Subsystem Modules Multiple Packages and /or Die on High Performance Organic Interposer/Substrate with System Connectors (Electrical: Card edge or Plugs, Optical: Fiber-optic Cable connectors) It’s an easy step to see how the integration extending to include organic interposers thus permits real HPC class systems on a business card sized module.

Bonding in Action

Summary 2.5/3D market is in the adoption cycle Drivers are: Moving from novelty to mainstream Drivers are: Heterogeneous integration SWaP Increasing performance Lower system costs First markets are: Logic – Memory Sensors Significant industry shifts will happen Silicon circuit cards with “Lego” blocks 2.5 and 3D integration is in the adoption cycle for markets that can get the most high leverage gain such as image sensors and logic-memory devices. These markets reap benefits in several areas that can’t be addressed by additional CMOS scaling alone (More Moore). The revolution of 3D is becoming the evolution of semiconductors and attracting applications with larger volumes and higher sensitivity to cost and risk.

New Silicon Sensor PDKs and Process Availability Adding PIM caps and HR poly resistors to baseline process

Austin Facility Overview 110 Employees: 90 in Ops and Engineering Over 150 production grade tools 68,000 sq ft Class 10 clean room 24/7 operations & maintenance Manufacturing Execution Systems (MES) IP secure environments, robust quality systems ISO certified/ITAR registered Full-flow 200mm silicon processing, 300mm back-end (Copper/Low-k) Process library with > 25000 recipes Novel materials (ALD, PZT, III-V, etc) Copper & Aluminum BEOL Contact through 193nm & IR lithography Silicon, SOI and Transparent MEMS substrates Electrical Characterization and Bench Test Lab Onsite analytical tools and labs: SIMS, SEM, TEM, Auger, VPD, ICP-MS, etc

2.5D Interposer Build and Assembly Flow

Si Interposers A key element to any 2.5D integration is of course a silicon interposer. Tezzaron has engineered a thick metal copper interconnect stack that enables longer wire lengths with high frequency signaling. A full PDK with DRC, LVS and parasitic extraction is available. Metal stacks up to 6 thick copper layers are supported. Gretchen this has the old drawing with 1um copper. We should change it to the diagram that shows the 2 um metals.

Interposer Parameters Layer Metal thickness R(mΩ/) at DC W L Cg (fF) M1 2μm 9.2 10 2 2.94 200 58 M2 1.83 21.0 M3 1.4 19.7 M4 0.919 13.9 TSV Diameter TSV Height Resistance Cg (fF) Filled 10μm 100μm 21.2mΩ 180 Conformal 80μm 300μm ~15mΩ ~600

Steps 1 & 2 Novati Nhanced Raw Wafer Build Interposer Frontside Process Frontside UBM

Steps 2, 3, 4 & 5 Nhanced Novati Process Frontside UBM Attach Carrier Grind Substrate Recess Substrate

Steps 5, 6 & 7 Novati Nhanced Recess Substrate Finish Backside Processing Nhanced Backside UBM Processing

Steps 7, 8 & 9 Nhanced Backside UBM Processing Attach Interposer Bump Singulate and Remove Carrier

Steps 9, 10 & 11 Nhanced Singulate and Remove Carrier Attach Interposer to Substrate Attach Die to Interposer

Steps 11, 12 & 13 Nhanced Attach Substrate Bump Attach Die to Interposer Underfill Die and Interposer

Apply TIM and Attach Lid Steps 13 & 14 Nhanced Apply TIM and Attach Lid Attach Substrate Bump

Supply Chain Donor Die Donor Die Bump Interposer UBM Topside Interposer UBM Bottomside Interposer Bump Interposer Underfill Donor Die Underfill Organic Substrate Substrate Bump TIM Package Lid Carrier Wafer Singulation Bond/Debond