High-Speed/Low Power At Architectural Level

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Presentation transcript:

High-Speed/Low Power At Architectural Level The Circuit Under Study Behavioral Simulations to Verify Functionality Speed & Area & Power Results, Through Synthesis with Synopsis, @ 1.6V Default in CMOSP18 Cell Library Xiao Xing

The Circuit Under Study

Behavior Simulations (Combinational)

Behavior Simulation (2-Stage Pipeline)

Behavior Simulation (4-Stages Pipeline)

Behavior Simulation (8-Stages Pipeline)

Behavior Simulation ( 2 Combinational Multipliers In Parallel)

Behavior Simulation (2 2-Stage Pipelines In Parallel

Version of Array Multiplier Purely-Combinational 2 Pipe-Lines 4 Pipe-Lines 8 Pipe-Lines 2 Combos In Parallel 2 2-Stage Pipelines In Parallel Area Combinational 5366.566 6626.903 9964.770 10009.5 13091.204 14.973.586 Sequential 2931.304 6460.256 13412.431 1496.144 7370.954 Total Cell Area 5366.568 9558.213 16425.031 23421.957 14587.317 22344.514 Frequency/Throughput 1 / 14.38 ns = 66 MHz 1/8ns = 125 Hz 1/4ns = 250 MHz 1/3ns = 333 MHz 1/15ns = 66 MHz 1/9ns = 111 MHz Power Cell Internal Power 3.9025mW (43%) 1.088 mW 3.2437 mW 6.6204 mW 656.6855uW (60%) 2.188 mW (73%) Net Switching Power 5.2012 mW (57%) 384.571 uW (26%) 814.7785 uW (20%) 908.6389 uW (12%) 431.1658 uW (40%) 817.109 uW (27%) Total Dynamic Power 9.1037 mW (100%) 1.4726 mW (100%) 4.0619 mW (100%) 7.5291 mW (100%) 1.0879 mW (100%) 3.0051 mW (100%) Cell Leakage Power 169.6141 nW 515.6460 nW 823.4979 nW 953.3696 nW 881.6794 nW 1.1654uW

Comparison of Total Cell Area

Comparison of Frequency/Through-Put

Comparison of Power

Summary 8-Stage Pipeline is the most Area, Power Consuming, but also the Fastest of all Array Multipliers Implemented While 8-Stages is twice of 4-stages in terms of area and Power, its only about 1.3 Times Better in Speed (Diminishing Return), confirming the prediction that one can NOT Gain Infinitely Speed, in Simply Increasing the number of Pipeline Stages With Parallelism, one Should Gain consistent Twice the Speed, at Twice the Area and Power Consumed; But Clock/Data Skew becomes a problem with Larger Parallelism, even if Power And Area is of no Issue 2 2-Stage Parallel Array Multiplier, is the 2nd Fastest, Most Power/Area Consuming; 4-Stage Pipeline come close to it in every department

Possible Enhancements Gate-Level Net List Simulation to Verify, real life Functionalities and Performances Correct the Synthesis Result for the Purely Combinational Array Multiplier Performance and cost of 4 and 8 Pipelines In Parallel

References [1] Jia Di, J. S. Yuan and R. DeMara, Improving Power-awareness of Pipelined Array Multipliers using 2-Dimensional Pipeline Gating and its Application on FIR Design, Integration, the VLSI Journal, Vol. 38,No. 3, February 2005 [2] Jan, M Raebey, Digital Integrated Circuits, 2nd Edition, Prentice Hall,2003 [3] John R, Calvert, Design of a Synchronous Pipelined Multiplier and Analysis of Clock Skew in High-Speed Digital Systems, NAVAL POSTGRADUATE SCHOOL MONTEREY CA , Dec 2000 [4] Daniel J. Sorin, Pipelining and Advanced Topics, http://www.ee.duke.edu/~sorin/ece152/lectures/7.3-pipelining.pdf, Jan 2005