Serial Multipliers Prawat Nagvajara Serial Bit-vector Multiplication Mapping Dependency Graph onto Signal Flow Graph (DG => SFG) A schedule that implies N-bit Adder Project Serial Multiplier Reading

Serial Bit-vector Multiplication Two nested-loop Algorithm For I in 0 to n-1 loop For J in 0 to n-1 loop … End loop; Compute inner loop using combination N-bit adder and iterate Outer loop in time It will take N clock cycles to complete Array multiplier does not work with clock. It is a combinational circuit

Dependency Graph equals Algorithm

A Version of Serial Multiplier (a0,a1,a2,a3,a4) Partial Sum AND gates b0, b1, …, b4 Serially carry N-bit Adder P0, P1, …, P4 serially Register

Mapping Dependency Graph Onto Signal Flow Graph (DG => SFG)

DG => SFG SFG dimension less than DG due to iteration in time We often linear project DG to obtain SFG, e.g., a line to a point in the adder example How do we compute the DG? Hyper plane of computations done at each clock cycle Schedule for the nodes. When and where they are computed

Mapping Multiplication DG onto an SFG carry b(t) D D D D D p(t)

Processing Element X_j Y_i AND Full Adder C_out C_in DFF PS_in PS_out CK

Another Version of Serial Multiplier x4 x3 x2 x1 x0 b0,…,b4 ‘0’ p0,p1,… Application Note: When t = 0, 1, 2, 3, 4 apply b0, b1, b2, b3, b4; When t = 5, 6, 7, 8, 9 apply ‘0’, to flush out p4, p5, …, p9

A Pipeline Mapping Multiplication DG carry b(t) D D D D D D D D D D p(t)

Processing Element X_j DFF Y_out Y_i AND DFF C_out Full Adder C_in DFF PS_in PS_out

A Pipelined Multiplier We will do an example of (111) * (111) = (110001)

Snapshots at t= 0, 1 1 1 1 1 1 1 1 1 1

Snapshots at t= 2, 3 1 1 1 1 1 1 1 1 1 1 1 1 1

Snapshots at t= 4, 5 1 1 1 1 1 1 1 1 1 1 1 1 1

Snapshots at t= 6, 7 1 1 1 1 1 1 1 1 1 1 1 1

Snapshots at t= 8, 9 1 1 1 1 1 1 1 1 1 1

Snapshot at t= 10 1 1 1 1 1

The Schedule Partial Sum computed at t=6 is an output at t=8 Carry computed at t=6 is an output at t=10 t=0 t=1 t=2 t=3 t=4 t=6 t=5

Pipeline Structure Temporal Parallelism Schedule that infers delay at edges of the signal flow graph Pipelining rate (bandwidth): The rate at which the data are piped into the array, e.g., the multiplier example has the rate ½ (every other clock cycle the multiplier bit is applied Latency: The time it takes to complete an algorithm

Is There Other Pipeline Multiplier?