COVER Full production should arrive today Test bench ready (Johan) Organize shifts for testing Test all boards ASAP to know the yield and possible problems Keep covers in place when installed on the detector Clean procedure Need extra cleaning on bottom? Remote programming Firmware version 10 Developing software Ready for test soon Georgios -> Vito

SERVICES MPOD ordered Patch panels and on-detector cabling (Johan) End of January Patch panels and on-detector cabling (Johan) Dense but feasible LV cover cables with different lengths Missing LV power connector Replace by smaller one with more pins ? Also few thinner cables due to the pin limit RJ45 needs careful planning How many different lengths? Storage behind rack ~1 meter

SRB Changes in connectivity and data flow FPGA event manager Input FPGA FESRB 4 groups of 4(8) links/covers 320(400)Mb/s Output 60kHz/straw => ~4MHz events => 4M * 2r/f * 48bits/word ~= 400Mb/s 4(8) links from covers covered by FESRB FPGA now mix of high-rate and low-rate covers Equalize data flow for 4 groups (FPGAs) Helps with data reordering in time Requires clock delay control for every line/cover Cable lengths Link to EVENT_MANAGER FPGA is 1.6Gb/s synchronous with TTC FPGA event manager Input 4 links of 1.6Gb/s with expected rate of 4*400Mb/s = 1.6Gb/s Significant reserve (factor 4) for clusters Data buffered in DDR3 memory 2/4/8GB Fluctuations removed Now 2 links 2.0Gb/s (2.5 with 8B10B) to VME and TRIGGER each Probably 1 enough 1 is reserve if data flow is higher then expected Ethernet is using RGMII instead of GXB (set of lower speed links instead of 1 Gb/s link) as there is not enough high speed links (almost) all important components integrated Compiled 4Gbit versus 2Gbit DDR3 chips Availability Price fluctuates a lot, currently 10-12USD/chip (from 8 in September) 2 DDR3 controllers or 1 is enough?

COVER CONTROL, DATA, SYNCH SRB – components L0 PROCESSOR L0 LOOK_UP TABLE L0 OUT VME INTF ON-LINE MONITOR LEMO TTC TTCRx COVERS TIME REMAP WORK DATA TO PC FARM COVER CONTROL, DATA, SYNCH EVENT PROCESSOR 2(4)GB DDR3

SRB – data flow VME 2.5 Gbit/s 16x2x320Mbit/s ~10Gbit/s 1.6 Gbit/s 2x Gbit ethernet

SRB - event manager FPGA U X FE LINK FIFO DDR3 buffer TRG 2.5G 2x FE LINK FIFO VME 2.5G 2x M U X FE LINK FIFO SRAM (remap) DDR3 buffer ETH 2x FE LINK FIFO SLOW CTL VME

SRB Estimation of schedule Delayed as some problems with new technology But now much better idea FPGA event_manager is (almost) ready for system integration Finalize/optimize pinout Add control BX reset, L1 primitives Requires extra link from VME/TTC FPGA Work on FESRB FPGA in January Expected to be fast Changes to current prototype chip 4 covers instead of 2 1.6Gb link to event_manager 4 programmable clock outputs Using high speed link with phase shift

SRB VME FPGA TRIGGER FPGA Schematics + PCB design Prototype April/May CPU part could be reused from ALTERA course ethernet, USB, memory, terminal, etc VME interface current one Add 2x2Gb/s input links and DDR3 buffer TTC control mostly reusable TRIGGER FPGA Probably only pin definition 2x2Gb/s input links Output 1 ethernet, 1 ‘SRB input’ link No demanding components Schematics + PCB design Feb-> March Prototype April/May