MOS Inverters 1

Digital IC Technologies sedr42021_1001.jpg Figure 10.1 Digital IC technologies and logic-circuit families.

Typical Logic Inverter VTC VIH VOH VOL VIL sedr42021_1002.jpg Figure 10.2 Typical voltage transfer characteristic (VTC) of a logic inverter, illustrating the definition of the critical points.

Noise Margins-1 the higherVIL and the lowerVOL, the better VIH VOL VIL VOH VIH the lowerVIH and the higherVOH, the better VIL VOH VIH VOL VIL Microelectronic Circuits - Fifth Edition Sedra/Smith

Noise Margins-2 NMH=VOH-VIH NML=VIL -VOL sedr42021_1002.jpg Figure 10.2 Typical voltage transfer characteristic (VTC) of a logic inverter, illustrating the definition of the critical points.

Logic Inverters time parameters tr: input rise time tf: input fall time tPHL: H to L propagation time tPLH: L to H propagation time tTHL: output H to L transition time tTLH: output L to H transition time sedr42021_1003.jpg Figure 10.3 Definitions of propagation delays and switching times of the logic inverter.

CMOS Inverter sedr42021_1004.jpg Figure 10.4 (a) The CMOS inverter and (b) its representation as a pair of switches operated in a complementary fashion.

CMOS Inverter Static Analysis sedr42021_0453.jpg Figure 4.53 The CMOS inverter. Microelectronic Circuits - Fifth Edition Sedra/Smith

Complementary n and p transistors-1 IDP ~0 (cutoff) sedr42021_0454a.jpg Figure 4.54 Operation of the CMOS inverter when vI is high: (a) circuit with vI = VDD (logic-1 level, or VOH); (b) graphical construction to determine the operating point; (c) equivalent circuit. Microelectronic Circuits - Fifth Edition Sedra/Smith

Complementary n and p transistors-2 sedr42021_0455a.jpg IDN~0 (cutoff) Figure 4.55 Operation of the CMOS inverter when vI is low: (a) circuit with vI = 0 V (logic-0 level, or VOL); (b) graphical construction to determine the operating point; (c) equivalent circuit. Microelectronic Circuits - Fifth Edition Sedra/Smith

pMOS load lines VGSp=-VSGp VDSp IDp =- IDSp IDn = IDSn VGSn VDSn V I V DD +V GSp DSn = - I DSp O IDn = IDSn VGSn VDSn V DSp I GSp =-2.5 =-1 V DSp I DSn =0 =1.5 V O I Dn =0 =1.5 V I = V DD +V GSp DSn = - I DSp V O = V DD +V DSp

CMOS Inverter Load Characteristics DD

Transistors operating regions sedr42021_0456.jpg to use VM instead of Vth Do not confuse with threshold voltage Figure 4.56 The voltage transfer characteristic of the CMOS inverter. Microelectronic Circuits - Fifth Edition Sedra/Smith

Current Behavior sedr42021_0458.jpg Figure 4.58 The current in the CMOS inverter versus the input voltage. Microelectronic Circuits - Fifth Edition Sedra/Smith

CMOS Inverter Noise Margins NMH =VOH-VIH =VDD-VIH NML=VIL -VOL =VIL -0 Very high margins !! sedr42021_1005.jpg Figure 10.5 The voltage transfer characteristic (VTC) of the CMOS inverter when QN and QP are matched.

CMOS Inverter Noise Margins sedr42021_1005.jpg when Vtp= -Vtn Equal Noise Margins: VM Figure 10.5 The voltage transfer characteristic (VTC) of the CMOS inverter when QN and QP are matched.

CMOS Inverter Dynamic Analysis-1 VGSn(t=0+)n=VDD VDSn(t=0+)n=VDD VGSn(t=0-)=0V VDSn(t=0-)=VDD sedr42021_0457a.jpg Figure 4.57 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) trajectory of the operating point as the input goes high and C discharges through QN; (d) equivalent circuit during the capacitor discharge. tPHLor tPLH refer to the output Microelectronic Circuits - Fifth Edition Sedra/Smith

CMOS Inverter Dynamic Analysis-2 By using iD= -C.(dvO/dt), and integrating it, an approximate solution can be reached (assuming the simplifying condition VTH=0,2XVDD): tPHL = 1,6.C/[kn.VDD ] = 1,6.C/[kn´.(W/L)n.VDD ] tPLH = 1,6.C/[kp.VDD ] = 1,6.C/[kp´.(W/L)p.VDD ] Obs. It is more important understand the dependences

Discharge and Charge sedr42021_1007a.jpg Figure 10.7 Equivalent circuits for determining the propagation delays (a) tPHL and (b) tPLH of the inverter.

CMOS Inverter Dynamic Analysis-3 Alternative form by average current, from t=0 to tPHL (or tPHL) tPHL= C.DV/IDn|aver = C. (VDD /2)/IDn|aver , where IDn|aver= [IDn(0)+ IDn(tPHL)]/2 t=0 (saturation): IDn(0)= kn.(VDD - VTH)2/2 t= tPHL (linear): IDn(tPHL)= kn.[(VDD - VTH)(VDD /2)- (VDD /2)2 /2] Obs. tpLH can be obtained similarly

Cascaded Inverters Capacitances- 1 sedr42021_1006.jpg Figure 10.6 Circuit for analyzing the propagation delay of the inverter formed by Q1 and Q2, which is driving an identical inverter formed by Q3 and Q4.

Cascaded Inverters Capacitances- 2 Polysilicon In Out Metal1 V DD GND PMOS NMOS 1.2 m =2l

Cascaded Inverters Capacitances- 3 sedr42021_1006.jpg 23

Cascaded Inverters Capacitances- 4 Bottom and Side-wall sedr42021_1006.jpg 24

Cascaded Inverters Capacitances- 5 Bottom and Side-wall sedr42021_1006.jpg 25

Cascaded Inverters Capacitances- 6 CGDO sedr42021_1006.jpg 26

Cascaded Inverters Capacitances- 7 CGDO and COX sedr42021_1006.jpg 27

Power Consumption Direct-path Power Dynamic Power Vin IC Vout ID C Vin L Vdd IC ID Direct-path Power Dynamic Power Vin Vout C L Vdd IC ID

Dynamic Power Dynamic Power >> Direct-path Power Pdyn= f.CL.VDD2  switching activity is critical Edyn= CL.VDD2  Energy required to charge and discharge CL