MPC8360 Micro Controllers 371-1-2403 Introduction Fall , 2010

Course Duties Attending all lab sessions is mandatory. (Approvals for not attending a lab will be given by the instructors only in special cases like reserve duty etc. A short written quiz will be conducted at the beginning of each Lab session. The quiz's material will be published in advance. Failing (less than 60) in the quiz will cause a zero lab grade in that lab session. At the end of each lab each student will get a “lab grade” according to his performance and knowledge during the lab. Final report submission. Final exam – must pass with grade greater than 56.

Grading Passing the final exam (exam grade > 55) is mandatory. In case of failure, the final course grade will be determined solely based on the exam. Section % Final report 15% Lab execution grade 40% Final quiz 45%

Syllabus Lab Number Topic Introduction MPC8360 Architecture ADS introduction CW introduction Programming model Registers and Instruction Set Assembly language 1 Breaking the 32bit Barrier 2 The Load Store Unit 3 Branching and Subroutines 4 Timers 5 Polling & Interrupts 6 DMA 7 Cache memories 8 Final Projext

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Course Objectives Introduction to the MPC8360 architecture. Assembly language of the PowerPC microprocessor family. Real time embedded coding for the MPC8360.

The MPC8360 MDS Processor Board The MPC8360EA MDS Processor Board is an application development system that provides a complete debugging environment for engineers developing applications for the MPC8360 series of Freescale processors

PC Connection To PC USB

MPC8360 A Simplified Block Diagram E300 Core QUICC Engine …. Communication Ports DDR/DDR2 Controller Interrupt Controller The QUICC Engine™ block handles communication tasks with the outer world. It supports a wide range of communication protocols including ATM, Ethernet, HDLC, TDM, and POS. This block offloads the communication tasks from the core thereby allowing it to do other system tasks. The E300 Core is the system's "brain" it executes instructions (computer programs) and manages the interaction between all the sub units. The core implements a 32-bit the architecture.

The dot (.) suffix enables the update of the CR register The Core Registers General-Purpose Registers (GPRs) 32 user-level GPRs that are 32 bits wide r0-r31 Condition Register (CR) The CR is a 32-bit user-level register that provides a mechanism for testing and branching. The dot (.) suffix enables the update of the CR register

The Core Registers XER register 32-bit register contains the summary overflow bit, integer carry bit, overflow bit.

The Core Registers XER register 32-bit register contains the summary overflow bit, integer carry bit, overflow bit.

The following suffixes can be added to a command: The Core Registers XER register 32-bit register contains the summary overflow bit, integer carry bit, overflow bit. The following suffixes can be added to a command: C - records a carry out in CA E - uses CA as an operand O - records an overflow in OV and SO

The Core Registers Link register (LR) The LR can be used to provide the branch target address and to hold the return address after branch and link instructions. The LR is 32 bits wide.   Count register (CTR) The CTR is decremented and tested automatically as a result of branch-and-count instructions. The CTR is 32 bits wide.

MPCxxx Instruction Set Command Variations Instruction Register (IR) Functional Description Affected Registers

MPCxxx Instruction Set 3 4 5 add r3,r4,r5

MPCxxx Instruction Set r0 = 0x00000001 r4 = 0x00001000 addi r4,r0,0x1 r4 = ? 0x00000001

MPCxxx Instruction Set EXTS (SIMM) = Extends Signed Immediate r0 = 0x00000001 r4 = 0x00001000 addi r4,r0,0xF000 r4 = ? 0xFFFFF000

MPCxxx Instruction Set r0 = 0x00000001 r4 = 0x00001000 addi r4,r0,0x1000 addis r4,r4,0x1000 r4 = ? 0x10001000