IEE5011 –Autumn 2013 Memory Systems Solid State Drives with Storage Class Memories Denni Kurniawan (0260813) Department of Electrical Engineering and Computer.

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Presentation transcript:

IEE5011 –Autumn 2013 Memory Systems Solid State Drives with Storage Class Memories Denni Kurniawan (0260813) Department of Electrical Engineering and Computer Science National Chiao Tung University

NCTU IEE5011 Memory Systems 2013 Outline Introduction Solid-State Drive NAND Flash Memory SSD Architecture NAND Flash Trend Storage Class Memory Conclusion Reference NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 Introduction NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 Introduction NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 Introduction NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 Solid-State Drive A Solid-state drive (SSD) is a storage device using to store data persistently. SSD does not contain moving mechanical disk as in hard-disk drive (HDD). NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 Solid-State Drive SSD Advantages No spin-up time Fast, random-access to data Use less power consumption Far more robust Silent NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 Solid-State Drive SSD Disadvantages High storage cost per gigabyte Lower drive capacities Relatively low write speed NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 NAND Flash Memory Source: Campordo et al. 2005 NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 NAND Flash Memory Read mode flash memory architecture Source: Campordo et al. 2005 NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 NAND Flash Memory Write mode flash memory architecture Source: Campordo et al. 2005 NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 NAND Flash Memory Erase mode flash memory architecture Source: Campordo et al. 2005 NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 SSD Architecture A memory controller task: To provide the most suitable interface and protocol towards the host and flash memories. To efficiently handle data, maximizing transfer speed, data integrity and information retention. NCTU IEE5011 Memory Systems 2013 Source: Takeuchi, 2009 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 SSD Architecture FTL is used to map logical blocks to their locations within physical flash memory. An FTL allows file systems and SSD to maintain the block interface of disks and control over how the flash is managed. Two types of FTL a log-based approach and mapping consecutive ranges. Wear leveling techniques rely on the concept of logical to physical translation. Bad Block Management module creates and maintains a map of bad blocks. NCTU IEE5011 Memory Systems 2013 Source: Takeuchi, 2009 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 NAND Flash Trend Source: Wei Hwang, NCTU NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 NAND Flash Trend Source: Wei Hwang, NCTU NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 NAND Flash Trend NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 NAND Flash Trend IEEE International solid-state circuit conference NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 NAND Flash Trend Source: Wei Hwang, NCTU NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 NAND Flash Trend Source: Wei Hwang, NCTU NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 Storage Class Memory Source: Takeuchi, 2008 NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 Storage Class Memory Source: Wei Hwang, NCTU NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 Storage Class Memory Source: IBM NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 Storage Class Memory Papers presented at Symposium on VLSI Technology IEDM (Int. Electron Devices Meeting) NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 Storage Class Memory Memory capacity vs. cycle time Source: Everspin technologies NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 Storage Class Memory Memory Endurance vs. cycle time Source: Everspin technologies NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 Storage Class Memory Read vs. Write Bandwidth Source: Wei Hwang, NCTU NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 Conclusion SSD based NAND flash technology successfully replace HDD as storage device. SCM is a new class that reduce boundaries between storage/memory technology. The features of SCM technologies should be: non-volatile, short access times (~DRAM like), low cost per bit (more DISK like), and solid state The goal of SCM development is to create compact, robust storage and memory systems with greatly improved cost/performance ratios relative to other technologies. NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 Conclusion There are many technologies that claim the best for SCM application such as PCRAM, RRAM, FeRAM, and MRAM, but all of them are still in the competition. NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 References F. Masuoka et al., “New ultra high density EPROMand flash EEPROM with NAND structured cell,” in IEDM Tech. Dig., 1987, pp. 552–555. J. K. Kim et al., “A 120-mm 64-Mb NAND flash memory achieving 180 ns/byte effective program speed,” IEEE J. Solid-State Circuits, vol.32, pp. 670–680, 1997. S. Aritome et al., “A reliable bi-polarity write/erase technology in flash EEPROMs,” in IEDM Tech. Dig., 1990, pp. 111–114. Fontana, R.E.; Decad, G.M.; Hetzler, S.R., "The impact of areal density and millions of square inches (MSI) of produced memory on petabyte shipments of TAPE, NAND flash, and HDD storage class memories," Mass Storage Systems and Technologies (MSST), 2013 IEEE 29th Symposium on , vol., no., pp.1,8, 6-10 May 2013 K. Takeuchi et al., “A56 nmCMOS 99mm 8 Gbit multi-level NAND flash memory with 10 Mbyte/sec program throughput,” in IEEE ISSCC Dig., 2006, pp. 144–145. K. Kanda et al., “A 120 mm 16 Gb 4-MLC NAND flash memory with 43 nm CMOS technology,” in IEEE ISSCC Dig., 2008, pp. 430–431. K. Takeuchi, “NAND successful as a media for SSD,” presented at the IEEE ISSCC, Tutorial T7, 2008. K. Takeuchi., Novel co-design of NAND flash memory and NAN flash controller circuits for sub-30 nm low-power high-speed solid-state drives (SSD), Journal of solid-state circuits, vol. 44, no. 4, 2009. G.Goodson & R. Iyer, Design tradeoffs in a flash translation layer', 2010. T. Tanzawa, T. Tanaka, K. Takekuchi, R. Shirota, S. Aritome, H. Watanabe, G. Hemink, K. Shimizu, S. Sato, Y. Takekuchi, K. Ohuchi, A compact on-chip ECC for low cost Flash memories. IEEE J. Solid-State Circuits 32(May), 662–669 (May 1997) G. Campardo, R. Micheloni et al., 40-mm2 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR Flash memory. IEEE J Solid-State Circuits. 35(11), 1655–1667 (Nov 2000) R. Micheloni et al., A 4Gb 2b/cell NAND flash memory with embedded 5b BCH ECC for 36 MB/s system read throughput, in IEEE International Solid-State Circuits Conference Dig.Tech. Papers, Feb 2006, pp. 142–143 NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)

NCTU IEE5011 Memory Systems 2013 References R. Micheloni, A. Marelly, K. Eshghi, "Inside solid state drives (SSDs)", Springer series in advanced microelectronics 37, Dordrecht. 2013. L.M.Caulfield, "Symbiotic solid state drives: Management of modern NAND flash memory", Unpublished Doctoral's Dissertation, University of California, United States. R.F.Freitas. W.W. Wilcke. Storage-class memory: the next storage system technology". IBM Journal of R. and D., 52(4/5):439–447, 2008. J.G.Yun, Y. Kim, H. Shin. "Single-Crystalline Si Stacked Array (STAR) NAND Flash Memory." Electron Devices, IEEE Transactions on 58.4 (2011): 1006-1014. B. Eitan, R. Kazerounian, A. Roy, G. Crisenza, P. Cappelletti, and A. Modelli, ‘‘Multilevel Flash Cells and Their Trade-offs,’’ International Electron Devices Meeting, IEDM Technical Digest, December 8–11, 1996, pp. 169–172. K. Gopalakrishnan, R. S. Shenoy, C. T. Rettner, R. S. King, Y. Zhang, B. Kurdi, L. D. Bozano, et al., ‘‘The Micro to Nano Addressing Block (MNAB),’’ IEEE International Electron Devices Meeting, IEDM Technical Digest, December 5–7, 2005, pp. 471–474. S. Raoux, G. W. Burr, M. J. Breitwisch, C. T. Rettner, Y.-C. Chen, R. M. Shelby, M. Salinga, et al., ‘‘Phase-Change Random Access Memory: A Scalable Technology,’’ IBM J. Res. & Dev. 52, No. 4/5, 465–479 (2008, this issue). S. Hudgens and B. Johnson, ‘‘Overview of Phase-Change Chalcogenide Nonvolatile Memory Technology,’’ MRS Bull. 29, No. 11, 829–832 (2004). B.C.Lee, ; P. Zhou; J. Yang; Y. Zhang; B. Zhao; E. Ipek.; O. Mutlu; D. Burger., "Phase-Change Technology and the Future of Main Memory," Micro, IEEE , vol.30, no.1, pp.143,143, Jan.-Feb. 2010 L. C. Tran, ‘‘Challenges of DRAM and Flash Scaling Potentials in Advanced Emerging Memory Devices,’’ Proceedings of the Seventh International Conference on Solid-State and Integrated Circuits Technology, October 18–24, 2004, pp. 668–672. J. D. Aasheim and Y. Yang, ‘‘System and Method for Achieving Uniform Wear Levels in a Flash Memory Device,’’ European Patent Application No. EP20030000541, 2003. NCTU IEE5011 Memory Systems 2013 Denni Kurniawan (260813)