Timing and Event System S. Allison, M. Browne, B. Dalesio, J Timing and Event System S. Allison, M. Browne, B. Dalesio, J. Dusatko, R. Fuller, A. Gromme, D. Kotturi, P. Krejcik, S. Norum, D. Rogind, H. Shoaee, M. Zelazny

Outline Overview – HW Block Diagram and Reqts Progress since April, 2006 Outstanding Issues Task List The Event Definition system - EDEFs

Timing Architecture ~ Linac main drive line FIDO SLC E MPG V G 119 MHz 360 Hz SLC MPG P N E T E V G I O C SLC events LCLS events LCLS Digitizer LLRF BPMs Toroids Cameras GADCs Old klystrons I O C E V R TTL m P P N E T S T B TTL-NIM convert. SLC Trigs

Hardware Block Diagram Early 2007 Commissioning Modulator Triggers Existing Control System Beam Path Acq and Calibration Triggers BPM FEE PADs and PACs Timing Crate Acc and Standby Triggers E V G F A N 1 F A N 2 P N E T I O C E V R I O C E V R 1 E V R 2 E V R 3 I O C 360Hz Fiducial RF Timing BPM Crates LLRF Crate 119MHz Clock Future MPS Fiber Distribution: Timing Pattern, Timestamp, Event Codes Beam Rate, Beam Path Triggers Triggers Trigger F A N 3 E V R 1 C A M 1 I O C 1 ... E V R 8 C A M 8 I O C 8 F A N 4 E V R 1 C A M 1 C A M 2 I O C 1 … E V R 4 C A M 7 C A M 8 I O C 4 Laser Steering Crate Profile Monitor Crate … …

Event Generator (EVG-200) Event Receiver (EVR-200-RF) Micro-Research Finland Oy SFP transceiver Optical signal to EVRs (fan-outs) RF input Event clock divided from RF EVG-200: /4, /5, ... /12 Recovered RF output Programmable outputs 5 TTL level 2 LVPECL level External trigger input SFP transceiver Optical signal from EVG (or fan-out) Line syncronisation input 360 Hz

Event System Requirements Event Generator IOC: Send out proper event codes at 360Hz based on: PNET pattern input (beam code and bits that define beam path and other conditions) Add LCLS conditions such as BPM calibration on off-beam pulses , diagnostic pulse etc. Future – event codes also based on new MPS and user input Send out system timestamp with encoded pulse ID from PNET Send out event pattern to be used by SLC-aware IOCs and conditional logic on the EVR IOCs Manage user-defined beam-synchronous acquisition measurement definitions Check for match between user meas definitions and input PNET pattern at 360Hz and tag matches in outgoing pattern MPS Algorithm Processors and Master Pattern Generator (MPG): Rate-liming logic including beam “burst” and “single-shot” modes Send out PNET pattern to EVG and CAMAC controls (for modulator triggers)

Event System Requirements, cont Event Receiver IOC: Receive event pattern 8.3 msec before corresponding pulse Set trigger delays, pulse widths, and enable/disable Set some trigger delays and enable/disables at 120Hz max based on the incoming pattern and local conditions on the IOC – list of conditions under determination Perform beam-synchronous acquisition based on tags set by EVG in the pattern Perform beam-synchronous acquisition for the SLC-aware IOC based on the PNET part of the event pattern Set event code per trigger (triggering done in HW when event code received) Process pre-defined records when specific event codes are received

Tallies for Early 2007 Commissioning # EVRs = 31 (mostly PMC) # IOCs with EVRs = 28 # EVR Fanouts = 4 # Hardware Triggers = 120 and counting All TTL except 2 NIM triggers for QDCs Most require short cables (except LLRF) EVR with clock not yet available All acquisition electronics using either internal clocks, clock output from the RF timing system, or other external clocks

Progress since April, 2006 Hardware problems identified by CPE engineers: 119MHz clock input – no divide-by-one available on EVG, special chip added to board to provide direct clock input Cannot use EVG AC-line input for 360Hz fiducial without mod to FPGA (or design a special EVG transition module) Procurement finished Two test stands equipped and available Identified EVR IOCs and triggers needed for early commissioning Added more people of various disciplines (all part- time) to timing team

Issues Way behind in all tasks, significantly: Interface control document Hardware testing – jitter, fanout testing, etc Software testing Beam-synch-acq implementation just begun Cabling plans and documentation Triggering conditions (when to trigger and which event code and delay to use) are pushing more logic from EVG IOC to EVR IOC Need a full-time timing system engineer

Tasks – Hardware and Low Level SW Finish hardware bench testing Finish PMC-EVR driver EVG sequence RAM programming at 360Hz EVR trigger attribute change logic at 120Hz Event pattern records and timestamp distribution on the EVR IOCs Finish cabling plans and documentation Installation in sector 20 and 21

Tasks: High-Level Software Beam Synchronous Acquisition Integration with SLC-aware BPM acquisition

Beam Synchronous Acquisition (BSA) EVG Event Definitions (EDEFs) are used for BSA EDEF includes: Beam code SLC PNET bits and LCLS Modifier bits # to average, # to measure Client or System name Permanent System EDEFs are always active 1Hz, 10Hz, Full, Single Shot, Feedback Available to all clients Client applications may reserve a Client EDEF Client receives EDEF # assignment on demand Client proceeds to fill out definition, then sets “GO”

Slots for 20 possible Event Definitions allocated User Defs Fixed Defs

Synthesizing the EVG Broadcast MPG PNET bits 0x0 0x0 0x0 MPG PNET bits 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 LCLS bits 0x0 0x0 0x3 0x0 Upon match, set “event bit(s)” EDEF EVG to EVR Broadcast 0x0 0x0 0x0 0x0 0x0 inclusion mask 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 exclusion mask 0x0 0x0 0x0 0x0 0x0 EVR IOCs

User interface for defining an Event Def

Beam Synchronous Acquisition EVG broadcast at 360Hz checks all active EDEFs against PNET / LCLS Modifier pattern For every pattern to EDEF match, EVG sets appropriate “event bit” EVR IOC BSA device data is fanned out to 20 buffers Identified by its EDEF # or system name Enabled/disabled for acquisition by its “event bit”

Example of Data Fanout 20 Buffers One for each EDEF 2800 samples per buffer