BVM Engineering College Electrical Engineering Department 2150907: Microprocessor and Microcontroller Interfacing Interrupts of 8051 Prepared by: 130070109015 130070109016 130070109017

Inside Architecture of 8051 External interrupts On-chip ROM for program code Timer/Counter Interrupt Control On-chip RAM Timer 1 Counter Inputs Timer 0 CPU Serial Port Bus Control 4 I/O Ports OSC P0 P1 P2 P3 TxD RxD Address/Data 8051 Microcontroller Block Diagram

I/O Services A single microcontroller can serve several devices. Two ways: Interrupt method An interrupt is an external or internal event that interrupts the microcontroller to inform it that a device needs its service. Polling method

Polling method The microcontroller continuously monitors the status of a given device. When the condition is met, it performs the device. After that, it moves on to monitor the next device until every one is serviced. The microcontroller check all devices in a round-robin fashion.

Interrupt method Whenever any device needs its service, the device notifies the microcontroller by sending it an interrupt signal. Upon receiving an interrupt signal, the microcontroller interrupts whatever it is doing and serves the device. The program which is associated with the interrupt is called the interrupt service routine (ISR) or interrupt handler.

The advantage of Interrupts The microcontroller can serve many devices. Each device can get service based on the priority assigned to it. The microcontroller can ignore (mask) a device request. The use of microcontroller is more efficient. Ex: in polling system, HERE: JNB TI, HERE wastes much of the microcontroller’s time.

Interrupt Service Routine For every interrupt, there is a fixed location in memory that holds the address of its ISR. The group of memory locations set aside to hold the addresses of ISRs is called the interrupt vector table

Table 11-1: Interrupt Vector Table for the 8051 ROM Location (Hex) Pin Reset 0000 9 External hardware interrupt 0 (INT0) 0003 P3.2 (12) Timer 0 interrupt (TF0) 000B External hardware interrupt 1 (INT1) 0013 P3.3 (13) Timer 1 interrupt (TF1) 001B Serial COM interrupt (RI and TI) 0023 

Six Interrupts in the 8051 Reset Two interrupt for the timers TF0, TF1 Two interrupt for external hardware interrupts INT0, INT1 Serial communication TI or RI There is a limited number of bytes for each interrupt. 3 bytes for reset 8 bytes for timers and external hardware interrupts If the service routine is too short to fit the ISR, an LJMP instruction is placed in the vector table to point to the address of the ISR. Programmers must enable these interrupts before using them.

IE (Interrupt Enable) Register EA IE.7 Disables all interrupts. If EA=0, no interrupt is acknowledged. If EA=1, each interrupt source is individually enabled of disabled by setting or clearing its enable bit. --- IE.6 Not implemented, reserved for future use. * ET2 IE.5 Enables or disables timer 2 overflow or capture interrupt (8952). ES IE.4 Enables or disables the serial port interrupt. RI or TI ET1 IE.3 Enables or disables timer 1 overflow interrupt. TF1 EX1 IE.2 enables or disables external interrupt 1. INT1 ET0 IE.1 Enables or disables timer 0 overflow interrupt. TF0 EX0 IE.0 enables or disables external interrupt 0. INT0 

Steps in Enabling an Interrupt To enable an interrupt, we take the following steps: Set EA=1. Enables all interrupts. If EA=0, no interrupt will be responded to, even if the associated bit in the IE is high. Enable each interrupt by setting its corresponding bit in IE.

External Hardware Interrupts The 8051 has two external hardware interrupts: EX0: INT0, Pin 12 (P3.2) EX1: INT1, Pin 13 (P3.3)  These two pins are used in timer/counter. INT is a trigger for hardware control (GATE=1). Timer/counter is enabled only while the INT pin is high and the TR control pin is set. They are enabled and disabled using the IE register. EX0 by IE.0 EX1 by IE.1

External Hardware Interrupts Upon activation of these pins, the 8051 gets interrupted and jumps to the vector table to perform the ISR. There are two activation levels for the external hardware interrupts: Low level triggered Falling edge triggered This is chosen by IT0/IT1 in TCON. On Reset, IT0 and IT1 are both low, making external interrupts low level-triggered.

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