DIGITAL 2 : EKT 221 RTL : Microoperations on a Single Register

Today’s Outline Multiplexer-based transfers Transforming Block Diagram to Detailed Logic Shift Registers Shift Registers with Parallel Loads Shift Registers with Parallel Loads and Hold

Multiplexer-based transfer

Microoperations on a Single Register Implement one or more microoperations with a single register as the destination of all primary results. The single register may also serve as a source of an operand for binary and unary operations. A simple technique using multiplexers for selection is introduced to allow multiple microoperations on a single register

Multiplexer-Based Transfers A register receives data transfers from more than 1 sources. A dedicated multiplexer is used to select the wanted input Example shows: If K1=1, R0 receives data from R1. If K1=0, R0 receives data from R2. R2 R1 R0 K2 K1 1 S 2:1 MUX n=4

Multiplexer-Based Transfers How do we represent this in RTL form? Written in if-then-else: If (K1=1) then (R0 R1), else if (K2=1) then (R0 R2). Written in RTL: R2 R1 R0 K2 K1 1 S 2:1 MUX n=4 K1:R0 R1, K1K2:R0 R2 Hardware connections from two source registers, R1 and R2, to one common destination register, R0. Selection between R1 and R2 must be based on the control variables K1 and K2.

Multiplexer-Based Transfers Analyse the diagram for input: *n.c : no change R2 R1 R0 K2 K1 1 S 2:1 MUX n=4 K1:R0 R1, K1K2:R0 R2 K1 K2 Load R0 content n.c 1 R2 R1

Transforming a Block Diagram into Detailed Logic 1 S 2:1 MUX n=4 Load Block Diagram Transforming a Block Diagram into Detailed Logic Q0 Q1 Q2 Q3 D0 D1 D2 D3 Load 2 to 1 MUX Y0 Y1 Y2 Y3 A0 A1 A2 A3 B0 B1 B2 B3 S CLK K2 K1 R1 R0 R2 Detailed Logic

Shift Registers

*CP: a common clock pulse input that activates the shift Shift Registers Shift Registers move data laterally within the register toward its MSB or LSB position In the simplest case, the shift register is simply a set of D flip-flops connected in a row like this: *CP: a common clock pulse input that activates the shift

Shift Registers Parallel Output Serial Input Serial Output Data input, In, is called a serial input or the shift right input. Data output, Out, is often called the serial output. The vector (A, B, C, Out) is called the parallel output.

Shift Registers T0 is the register state just before the first clock pulse occurs T1 is after the first pulse and before the second. Initially unknown states are denoted by “?” Complete the last three rows of the table CP In A B C Out T0 ? T1 1 T2 T3 T4 T5 T6 1 1 1 1 1 1 1 1

Shift Registers with Parallel Load The shift register shown earlier has no control input, thus data is always shifted on clock pulse. How to make the shift registers more controllable? E.g. shifts only on select positive clock edges. Shift operation can be controlled through D inputs of the FFs, rather than through the clock inputs CP.

Shift Registers with Parallel Load By adding a mux between each shift register stage, data can be shifted or loaded If SHIFT is LOW, A and B are replaced by the data on DA and DB lines, else data shifts right on each clock. SHIFT IN Dn A0 A1 Selector 2 to 1 MUX Serial Input 1 1 1

Shift Registers with Parallel Loads and Hold But what if we want to hold to the current data, meaning no shift or no loading of new data? The design must have 2 controls: For the SHIFT For the LOAD Function Table for the Register of Fig 7-10 SHIFT LOAD OPERATION No Change 1 Load Parallel Data X Shift down from Q0 to Q3 We use an AND gate to disabled the Load input, so we mark with don’t care condition

Shift : Q sl Q, Shift Load : Q D 4-bit SHIFT REGISTER WITH PARALLEL LOAD AND HOLD OPERATION In Register Transfer Language: Shift : Q sl Q, Shift Load : Q D Control inputs AND gates: Enables the Shift operation Enables the input data Restores the contents of reg. when no operation 1 2 3 1 2 3 1 2 3 1 2 3 Figure 7-10 M. Morris Mano LOGIC AND COMPUTER DESIGN FUNDAMENTALS

Shift Registers with Parallel Loads and Hold 1 2 3 Shift Registers with Parallel Loads and Hold S = 0, L = 0 : AND3 in each stage is enabled The output of each FF is applied to its own D input. A +ve transition of CLK restores the contents of reg. Output Qi is unchanged

Shift Registers with Parallel Loads and Hold 1 2 3 Shift Registers with Parallel Loads and Hold Shift Load : Q D S = 0, L = 1 : AND2 in each stage is enabled The input Di is applied to D input of corresponding FF. Next +ve transition of CLK transfers the parallel input data into reg. Output Qi = Di

Shift Registers with Parallel Loads and Hold 1 2 3 Shift : Q sl Q, S = 1 : AND1 in each stage is enabled When +ve edge occurs on CLK: Data from serial input SI to be transferred to FF Q0, Output Q0 to be transferred to FF Q1, …and so on down the line.

Bidirectional Shift Register Unidirectional Register Capable of shifting in only one direction (like what we have discussed in last lecture) Shift on clock pulse Shift & Load Shift, Load & Hold * shift occurs in one direction only Bidirectional Register A register that can shift in both directions Shift Left (sl) Shift Right (sr) And at the same time is capable of HOLD and LOAD

Bidirectional Shift Register By placing a 4-input multiplexer in front of each D flip-flop in a shift register, we can implement a circuit with shift right, shift left, parallel load, hold. Each stage consists of a D-FF and 4:1 multiplexer S1 S0 Register Operation No change (hold) 1 Shift Left Shift Right Parallel Load S0 S1 A0 A1 A2 A3 4 to 1 mux 1 2 3 D

Bidirectional Shift Register How do we represent his in RTL?? S1 S0 Register Operation No change (Hold) 1 Shift Left Shift Right Parallel Load S1S0 : Q S1S0 : Q sl Q S1S0 : Q sr Q S1S0 : Q D

Bidirectional Shift Register Let’s analyze the one stage diagram of a Bidirectional Shift Register with parallel load. S1 S0 Register Operation No change (Hold) 1 Shift Left Shift Right Parallel Load

4 Bits Bidirectional Shift Register with Parallel Load Serial outputs: (Right Shift) (Left Shift)

Bidirectional Shift Register Shift registers can also be designed to shift more than a single bit position right or left Shift register can be designed to shift a variable number of bit positions specified by a variable called a shift amount.

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