Basic Delay in Gates Definitions tprop,fall Vin tprop,rise Vout trise tfall t Definitions tprop,fall / tprop,rise: 50% swing to 50% swing trise: 10% to 90% tfall: 90% to 10% Want to know: “how fast will design run” Note that trise tfall and tprop,rise  tprop,fall Usually consider: worst prop. delay Also, not worry about rise/fall Digital Design Review

Critical Path Analysis “How fast will this run?” B A C Q D E F Critical path If we change input, how long before output has correct result? Example: responds to A much faster than D Want to know longest time or critical path Not all gates equal: add up delay different gates / different technologies Digital Design Review

Input “glitches” Which happens? Depends: Technology could be t B F ? or Which happens? Depends: Technology How narrow pulse is relative to tprop, trise, tfall Digital Design Review

Glitches (Transients) B C A F Consider: What is the output? For static inputs: F=AA’=0 Single rising edge on A Pulse generator? Point: Inputs to comb. logic change  Transient period outputs fluctuate before final stable value A B C F Digital Design Review

Hazards/False Outputs Definition Output takes on a value that is not predicted by the Boolean expression for either old or new inputs Dealing with Hazards Circuits where only a single input changes at a time Include redundant terms (in k-map) Can eliminate hazards Synchronous design Signals only sampled on clock Period made long enough to be past transients Digital Design Review

Variations in Gate Delays Gate delay variation due to Temperature Vcc changes (imperfect power supply) Process variations Loading of gate vs. fast slow Digital Design Review

4. Sequential Circuits Digital Design Review

Complex Algorithms Require Digital Memory Elements Series of operations to be performed Order, timing important Storage for intermediate results Means we have memory Digital Memory Elements Latches Flip-flops SRAM, DRAM Digital Design Review

SR Latch Memory requires feedback Circuit has two stable states Can control with R/S inputs R Q Q’ S Digital Design Review

SR Latch To see stability... Can repeat for Q=1 and Q’=0. Same thing. R Q Q’ S 1 1 Digital Design Review

SR Latch “Set” Operation. 1 1 R Q Q’ S 1 1 1 Digital Design Review

SR Latch “Reset” Operation. 1 1 1 R Q Q’ S 1 1 Digital Design Review

SR Latch Transition Table R S Qnext Q 1 Undefined R Q Q’ S R Q S Q’ Q 1 Undefined R Q Q’ S R Q S Q’ Digital Design Review

SR Latch Summary Features Problems? Provides 1 bit of memory Control by temporarily raising S or R Problems? Output can change at any time when S/R change Think about glitches! Inconvenient to have two inputs to control How do we store just the bit on a line? Digital Design Review

Gated Latch Circuit responds when Gate=1 Q R Q S Q’ S Q’ G S Gate Circuit responds when Gate=1 Sometimes called a “transparent latch” or a “lodable latch” Digital Design Review

D-Latch Stores value on input D when G is high Q D Q S Q’ Q’ G Gate Stores value on input D when G is high Keeps old value otherwise Now we can store a value, just when we want Digital Design Review

Using Latches Any problems? Level sensitive Consider “toggle” circuit Output: 10 or 10 each time we assert Gate Will this work? Q D G Gate F Digital Design Review

Toggle Circuit Timing Circuit oscillates  Bad Q D G Gate F Gate D F Circuit oscillates  Bad Feedback with gated latch is difficult Digital Design Review

Master/Slave Flip Flops Idea Use two latches to get “edge” sensitive behavior Master Slave Q1 D Q D Q D Q G G clk D Q Edge sensitive latch called a “flip flop” clk Digital Design Review

Flip Flop Operation (1) When clk=1, only first latch is transparent Q D G Q1 Master Slave clk 1 1 1 When clk=1, only first latch is transparent Transitions on D only go through first latch! Digital Design Review

Flip Flop Operation (2) Consider storing a 1 in the flip flop Q D G Q1 Master Slave clk 1 1 1 1 1 Consider storing a 1 in the flip flop The bit got stored and sent to the output on a falling edge of clk (1=>0) Kind of like an “airlock” Make rising edge device with another inverter Digital Design Review

Utility of Flip Flops Example toggle circuit: Q  D only on 01 transition of clk Oscillation does not occur Can store 1 bit, sampled at an edge Q D clk F Digital Design Review

Flip Flop Timing D Q clk tsetup thold tclk-q (a) tclk-a Time until new latched value appears at output (b) tsetup Time before clock that D must be stable (c) thold Time after clock that D must be stable Digital Design Review

Flip Flop Timing: tclk-q D Q Q’ Extra inverter makes + edge sensitive. clk (a) tclk-q : Time for new output to appear on Q Gate gets to slave, value propagates through Digital Design Review

Flip Flop Timing: tsetup D Q Q’ clk (b) tsetup: Time D must be stable before clock Slave becomes transparent. Correct value must be at input! Time to go through master stage. Digital Design Review

Flip Flop Timing: thold Q Q’ clk (c) thold: Time D must be stable after clock Master latches. Should be value there at clock. Time to lower gate on master. Digital Design Review

Registers Definition Example Storage element One or more flip flops Four D flip flops in parallel: 4 4 D Q clk Digital Design Review

Types of Registers (1) Loadable Register Standard flip flop (or register) loads on every clock May want to selectively load input One idea: Problems? Adds delay to clock “clock skew” What about glitches? Q D clk EN CLK Digital Design Review

Types of Registers (2) Loadable Register Better way Q D CLK EN 1 EN Q 1 EN Q D Digital Design Review

Types of Registers (3) Shift Register Uses? Extensions: Enable, Direction, Parallel Load, Clear, ... Q D Sin Q0 Q1 Q2 Q3 CLK Digital Design Review

Counters Implementation Synchronous circuit made from a register Steps up or down on each clock edge Input (next value) computed from output (current value) +1 block from half adders Q D CLK +1 Digital Design Review

State Memory (register) Synchronous Circuits General synchronous circuit Counter State Machine Q D Input Forming Logic Next State State Memory (register) Comb. Logic Current State Digital Design Review

Synchronous Circuit Design Designing a General Counter State transition table Current state  Next state Boolean eq. for next_state = F(curr_state) Place flip flops between D Q F NS CS Digital Design Review

Generalization of Sync. Circuit Finite State Machine (FSM) Can be used to realize general sequential algorithms Moore outputs (depend only on state) Mealy outputs (depend on state and inputs) Current State Q D Input Forming Logic Next State Output Forming Logic Inputs Outputs For Mealy Outputs Digital Design Review

Generalization of Sync. Circuit Finite State Machine (FSM) Input Forming Logic Q D Output Forming Logic Outputs Next State Current State Inputs For Mealy Outputs Digital Design Review

FSM Design Process Similar to Counter Input Forming Logic Q D Output Forming Logic Outputs Next State Current State Inputs For Mealy Outputs Process Similar to Counter Write state transition table Implement using comb. logic Write truth-table or Boolean eq. for output logic Insert registers Digital Design Review

State Graphs Graphical representation of a state transition table Helps you visualize FSM operation Value in state register Current State Next State 00 01 10 11 Q1 Q0 N1 N0 1 Digital Design Review

Inputs Represented with labels (signal name) on arc Means if sig=1, take the path (arc) clr inc’ 00 inc inc clr inc’ clr inc’ 01 11 clr inc inc 10 inc’ Digital Design Review

Proper State Graphs Conflict-free State Graph Complete State Graph Only one possible next state for all possible inputs Is previous counter with inputs conflict free? Solve by introducing priority. Complete State Graph All next states are specified. “Incomplete” means we have omitted some cases inc 10 11 What happens when inc=‘0’ in 10? Digital Design Review

Outputs Put names of asserted signals next to (or in) state bubbles A / MID 00 01 10 11 TERM Means MID=1 in state 01 when A is asserted “Mealy output” Means signal TERM=1 in state 11 (0 otherwise) “Moore output” Digital Design Review

Example Sequence recognizer “011” (Moore) Xin S0 X’in Xin Xin Seq. Rec. clk X’in Z S1 X’in Z S3 X’in Xin Xin S2 Digital Design Review

Example Sequence recognizer “011” (Mealy) Xin S0 X’in Xin Seq. Rec. clk Xin/Z Z S1 X’in X’in Xin S2 Digital Design Review

One-Hot State Machines Definition More than one state, multiple flip flops for state “One hot” means only one flip flop active (stores a 1) at a time Uses? Simpler to design by hand Finding next state logic tedious for very many states Can eliminate output glitches Digital Design Review

One Hot Example go’ State transition table A go stop / Y run’ stop’ B CS NS X Y A 1 B go run stop CS NS X Y go run stop CS NS X Y A 1 B C D go run stop CS NS X Y A 1 B C D go run stop CS NS X Y A 1 B C A go stop / Y run’ stop’ B D X run C Digital Design Review

One Hot Example A go’ D stop A Q D State transition table A go B run’ CS NS X Y - A 1 B C D B Q D X B run C Q D C D stop’ D Q D stop Y Dns = Ccs + Dcs stop’ Ans = Acs go’ + Dcs stop Bns = Acs go + Bcs run’ Cns = Bcs run Digital Design Review

One Hot Example Glitches? Mealy output Y Can have glitch go’ D stop A Glitches? Mealy output Y Can have glitch Moore output FF does single trans. from CS to NS No glitch Q D A go B run’ B Q D X B run C Q D C D stop’ D Y Q D stop Y Digital Design Review

Summary Number Systems / Binary Encoding Boolean Algebra Combinational Circuits Sequential Circuits Fundamental concepts and terms we need for the rest of the course. Digital Design Review