Quad D Flip Flop Index Circuit Error Judgment Scenario

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Presentation transcript:

Quad D Flip Flop Index Circuit Error Judgment Scenario 2017-04-05 Sanghee Byun

Circuit D1 D2 D3 D4

Error Judgment Scenario 1. All Q set Low /MR CLK D Q Initial State L X -> Initial State : It means all Q(Q0,1,2,3) set Low. Is it Right? 2. When an error occurs, The following signal input to D0, CLK 3. The above signal input 4 times, It means something wrong. So Q3 output High. Error Count /MR CLK D Q 1 (D0, Q0) H ↑ 2 (D1, Q1) 3 (D2, Q2) 4 (D3, Q3) -> If Q3 output High, It consider an error signal. -> At the First Count, Q1,2,3 stay Low? -> Is there any possibility of not proceeding like the truth table?