IT IS ABOUT : Programmable Logic PAL, PLA

GUIDED BY:- Prof. Viharika Patel PRESENTED BY:- Rifat pothigara 130130111096 EC-B

Programmable Logic Array PLAs Programmable Logic Array Pre-fabricated building block of many AND/OR gates (or NOR, NAND) "Personalized" by making/ breaking connections among the gates. General purpose logic building blocks.

PLA

PLA

PLA A 3×2 PLA with 4 product terms.

Design for PLA: Example Implement the following functions using PLA F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A Input Side: 1 = asserted in term 0 = negated in term - = does not participate Personality Matrix Outputs Inputs Product t erm Reuse of erms A 1 - B C F 2 3 A B B C A C Output Side: 1 = term connected to output 0 = no connection to output

Example: Continued F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B Personality Matrix

Constants Sometimes a PLA output must be programmed to be a constant 1 or a constant 0. P1 is always 1 because its product line is connected to no inputs and is therefore always pulled HIGH; this constant-1 term drives the O1 output. No product term drives the O2 output, which is therefore always 0. Another method of obtaining a constant-0 output is shown for O3.

BCD to Gray Code Converter Minimized Functions: W = A + B D + B C X = B C' Y = B + C Z = A'B'C'D + B C D + A D' + B' C D'

Product terms cannot be shared ! A B C D A BD 4 product terms per each OR gate BC BC’ Product terms cannot be shared ! B PLA achieves higher flexibility at the cost of lower speed! C BCD AD’ BCD’ W X Y Z

PALs Programmable Array Logic a fixed OR array.

PAL Logic Implementation Design Example: BCD to Gray Code Converter K-maps Truth Table A 1 B C D W X Y Z AB CD 00 01 11 10 D B C A X 1 K-map for W Y Z Minimized Functions: W = A + B D + B C X = B C Y = B + C Z = A B C D + B C D + A D + B C D

PAL Logic Implementation Programmed PAL: A B C D A B C D A BD BC B C BCD AD W X Y Z Minimized Functions: W = A + B D + B C X = B C Y = B + C Z = A B C D + B C D + A D + B C D 4 product terms per each OR gate

PAL Logic Implementation Code Converter Discrete Gate Implementation B C A D W X Y 2 Z 1 4 3 5 1: 7404 hex inverters 2,5: 7400 quad 2-input NAND 3: 7410 t ri 3-input NAND 4: 7420 dual 4-input NAND 4 SSI Packages vs. 1 PLA/PAL Package!

PLA Logic Implementation Another Example: Magnitude Comparator A K-map for EQ 1 AB CD 00 01 11 10 D B C GT L T NE EQ NE LT GT ABCD AC BD ABD BCD ABC A B C D

PALs and PLAs What is difference between Programmable Array Logic (PAL) and Programmable Logic Array (PLA)? PAL concept — implemented by Monolithic Memories AND array is programmable, OR array is fixed at fabrication A given column of the OR array has access to only a subset of the possible product terms PLA concept — Both AND and OR arrays are programmable

PALs and PLAs Of the two organizations the PLA is the most flexible One PLA can implement a huge range of logic functions BUT many pins; large package, higher cost PALs are more restricted / you trade number of OR terms vs number of outputs Many device variations needed Each device is cheaper than a PLA

Thank you…….