FMC adapter status Luis Miguel Jara Casas 5/09/2017

FMC adapter: DP1 RJ45 FMC connector DP2 JTAG Connection with PCIe in XPressK7 board, from FPGA(no room for cables) ~18mm ~7mm DP1 LEMO RJ45 ~ 20mm FMC connector DP2 ~ 20mm AC coupling Signal multiplexing Level converters Regulators Clock generation ADC EEPROM … ~ 17mm JTAG LEMO LEMO LEMO ~7mm ~7mm ~7mm

Status: Interface DisplayPorts-FMC connector: Ongoing DP1 Interface DisplayPorts-FMC connector: Ongoing Some doubts about multiplexing of signals, AC coupling and signal integrity depending on final SCC pinout. DP2 LEMO Lemo connectors interface with FMC connector: DONE RJ45 RJ45 interface with FMC connector: DONE FMC connector JTAG JTAG interface with FMC: to be decided which JTAG connector to use. Ongoing, pending to close depending on the decisions for DisplayPorts. Clock generation in FMC Two clocks added (GTXs reference and one for the general fabric), I2C programmable, more clocks can be added under request. EEPROM EEPROM included for compliance with other boards.

DisplayPorts Interface DisplayPorts with FMC adapter: Taking as a reference the DRAFT schematics of SCC (below): some data lanes are also used for external clocks (serializer and CMD clock). Study of the proposal of being able to use the same DisplayPort connector on the DAQ side for both CMD+DATA as well as CLK+HIT_OR from firmware. In order to multiplex this signals in the FMC board via firmware, high speed bidirectional analog switches are needed: Data are CML while external clocks are LVDS. Data and clocks have different directions. DisplayPort pinout in SCC draft version

DisplayPorts Interface DisplayPorts with FMC adapter: Taking as a reference the DRAFT schematics of SCC (below): some data lanes are also used for external clocks (serializer and CMD clock). Study of the proposal of being able to use the same DisplayPort connector on the DAQ side for both CMD+DATA as well as CLK+HIT_OR from firmware. FMC adapter card SCC DP1 LEMO RJ45 FMC connector DP2 JTAG LEMO LEMO LEMO

High speed analog switch DisplayPorts One level of switches in two data pairs: First one in order to provide flexibility from firmware point of view, being able to use both DisplayPorts in the FMC adapter for CMD+DATA or CLK+HIT_OR Second in order to be able to provide external serializer and command clock in some of the data lanes (in two of the high speed differential pairs). FMC adapter card SCC DP1 FPGA TX High speed analog switch AC coupling CML buffer CML DATA or HIT_OR GTX DATA LVDS Sel2 RX LVDS Buffer HIT_OR In order to provide flexibility and choose from firmware which DP connector goes to which SCC DP connector

DisplayPorts Two levels of switches in two data pairs: First one in order to provide flexibility from firmware point of view, being able to use both DisplayPorts in the FMC adapter for CMD+DATA or CLK+HIT_OR Second in order to be able to provide external serializer and command clock in some of the data lanes (in two of the high speed differential pairs). FMC adapter card SCC High speed bidirectional analog switch LVDS Clock Buffer DP1 FPGA TX EXT_CLK (SER,CMD) High speed analog switch AC coupling CML buffer CML Sel1 GTX DATA or HIT_OR DATA LVDS Sel2 RX Buffer HIT_OR In order to provide flexibility and choose from firmware which DP connector goes to which SCC DP connector

DisplayPorts Problems and questions of this configuration: DisplayPort pinout in SCC draft version Problems and questions of this configuration: AC coupling after the analog switches (operating range of analog switches can be exceeded if used in SP chains). Signal integrity of the data lanes: Ron of high speed bidirectional switches around 8Ω. Possible parasitic C and L in this switches. Layout: routing more complex. Recommendations from signal integrity experts at CERN: data lanes the most straight forward connected to multi-gigabit transceivers. If signal integrity is a real problem, possible solutions: Giving up to the flexibility of being able to choose which DisplayPort in the FMC adapter goes with which one in the SCC would provide two data lanes without any analog switch interface. The multiplexing could be implemented with jumpers if needed. Give up with that flexibility just for one of the HIT_OR pairs, HITOR3, so GTX0 doesn’t go through any analog switch.

DisplayPort: NTC Negative Temperature Coefficient thermistor (NTC) is included in the SCC card and connected to pins 13 and 14 of DP1 in SCC card. In the FMC adapter card, the voltage drop in this resistor is amplified and the output is ADC converted. Converter is controlled via I2C. Resistor network and amplifier of voltage drop NTC pins (coming from DisplayPort) 4 channel 12 bit ADC ADC control and readout via I2C FMC connector

Frequency programming for each output channel via I2C Clock generation in FMC adapter Clock resources in XPressK7 are not enough. Also a clock reference is needed for GTXs PLLs. A clock multiplier is included in the FMC adapter, with two clock outputs available: One connected to GTX clock reference pin. The second connected to MRCC driver in FPGA for general purpose. The output frequency can be programmed via I2C Clocks can be synchronized with an external signal if needed. CLK_GTX_REF FMC connector Sync clock Crystal oscillator x2 Clock multiplier CLK_GEN_PURPOSE Frequency programming for each output channel via I2C Clock output can be programmed from 0.001 to 1028MHz It fulfils the clock requirements needed for clock reference signals on GTXs (see back-up slides)

Voltage selection with jumpers Trigger IO 4 x LEMO: 4 Lemo connectors (2 RX and 2 TX) connected to a transceiver with configurable voltage translation. MMC3 taken as a reference LEMO TX FMC connector LEMO 4-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation TX LEMO RX LEMO RX Voltage selection with jumpers

Trigger IO RJ45: EUDET Telescope family (test-beam infrastructure) uses RJ45 connectors for trigger and handshake communication with the telescope/trigger devices. MMC3 taken as a reference FMC connector Drivers and receivers RJ45

EEPROM Included just in case the adapter is used with a Xilinx evaluation board for FMC Standard compliance (VITA 57.1). For these boards, the EEPROM is queried at power on. Problems detecting the presence of an FMC mezzanine in case not mounted. Not need to be mounted for other boards. FMC connector EEPROM memory ADC control and readout via I2C Write protection via jumpers

JTAG FMC connector Layout From RD53A, all JTAG pads are pulled-up or down ON-CHIP according to the standard, except the test reset pad TRST_B. Pending to decide which JTAG connector type. FMC connector Pinout of the FMC connector takes into account the resources of the XpressK7 (allocation of different drivers, power sources, clock capable pins…) Some pins in Column J are avoided as they are non-FMC compliant signals in the XPressK7. Pinout changes depending on topics discussed previously. Layout Layout will be done by CERN PCB workshop and reviewed by ourselves once a stable version of the schematics is finished.

Thank you!

Backup slides

Clock reference for MGTs: MGTs in XPressK7 board are already connected to oscillators, needed as a reference, but in the case of the MGTs connected to the FMC, no oscillator is mounted. Oscillator used as a clock reference for MGTs connected to PCIe The oscillator connected to the quad MGT bank that is wired to the FMC connector is not mounted (but clock of the previous MGT bank can be used, 100MHz, external clock can source up to 3 GTX quads)

Jitter on the reference clock has a disastrous effect on the channel’s quality, can be far worse than poor a poor PCB layout. QPLL and CPLL locks in the reference clock, so jitter on the reference clock results in jitter in the serial data clock. The prevailing effect is in the transmitter, which relies on this serial data clock. The receiver is mainly based on the clock it recovers from the incoming data stream, so it is less sensitive to jitter. Transceiver reference clock checklist from Xilinx 7 series FPGAs GTX/GTH Transceivers User Guide (UG476)

VOLTAGE SWING of the reference clock: -0.5V min, 1.32V max REFERENCE CLOCK characteristics: OURS is -2 (DS182 Xilinx data sheet)