Vertically-integrated CMOS Geiger-mode avalanche pixel sensors L. Pancheri, P. Brogi, G. Collazuol, G.-F. Dalla Betta, A. Ficorella, P.S. Marrocchesi, F. Morsani, L. Ratti, A. Savoy-Navarro University of Trento & TIFPA University of Siena & INFN Pisa University of Padova & INFN Padova University of Pavia & INFN Pavia Laboratoire APC, University Paris-Diderot/CNRS Paris 14th Topical Seminar on Innovative Particle and Radiation Detectors (IPRD16) Siena, Italy, October 3-6, 2016
APiX2 project “Development of an Avalanche Pixel Sensor for tracking applications” Funded by INFN – CSN5 Project coordinator: Pier Simone Marrocchesi, INFN Pisa and University of Siena Partners: TIFPA and University of Trento, INFN Pavia and University Pavia, INFN Padova and University of Padova, Laboratoire APC, Université Paris-Diderot/CNRS
Outline Introduction Sensor architecture Experimental results Summary and future perspectives
APiX particle detector concept Quenching Particle detection Discriminators Coincidence detector Dark counts Two Geiger-mode avalanche detectors (SPADs) in coincidence: DCR = DCR1 DCR2 2DT In-pixel coincidence: not feasible in SiPM optimized process (Hamamatsu, FBK, SensL …) Integrated electronics is needed: CMOS process V. Saveliev, US Patent. 8,269,181, 2012 N. D’Ascenzo et al., JINST 2014
Avalanche detectors – cross section Standard 150nm CMOS process – no modifications Avalanche diodes in deep nwell: isolated from substrate Type 1: Shallow step junction Active thickness ~ 1μm Type2: Deep graded junction Active thickness ~ 1.5μm L. Pancheri et al., J. Selected Topics Quantum Electron, 2014
Single-photon timing resolution Measured on 10-μm devices, with blue laser (470nm), 70ps FWHM Type 1: 60ps FWHM Type 2: 170ps FWHM
Proof-of-concept demonstrator 2-layer pixel cross section: Electronic readout on both layers Metal shielding from optical cross-talk Vertical interconnection by bump bonding
Pixel architecture Pixel enable/disable Pulse shortening: reduces the rate of accidental coincidence Programmable pulse width: 750ps, 1.5ns, 10ns
Pixel architecture: storage In-pixel 1-bit memory Output register for fast data output
Sensor floorplan Wire bonding pads on chip 2: pre-integration test. Bottom chip Top chip Wire bonding pads on chip 2: pre-integration test. Final assembly Top chip Bottom chip
Pixel array 16 x 48 pixel array Pixel size: 50μm x 75μm Splittings in detector type and area Bump bonding pad 30μm x 30μm 35μm x 35μm 40μm x 40μm 43μm x 45μm Pixels with different detector area (unshielded) Pixels with shielded detectors
Sensor micrographs Bottom chip Top chip
Bottom chip - Micrographs Shielded Unshielded
Bottom chip - Micrographs
Breakdown voltage uniformity Measurements on 5 sample chips x 2 types x 196 devices per chip Very good uniformity on-chip (s < 20mV) Large difference (1V) between different chips for type 1
Dark Count Rate Distribution VEX = 3.3V VEX = 3.3V Cumulative distribution, combined measurements on 3 chips 600 devices for largest size, 72 for smaller ones Median DCR = 2.2kHz for largest cell size of both types
Crosstalk characterization Crosstalk coefficient CRm = DCRe ∙ DCRd ∙ 2∆T + K ∙ ( DCRe + DCRd ) Emitter (fixed) Detector (scan) Crosstalk map – Type 1, 25µm thickness
Crosstalk vs substrate thickness
Vertically-integrated assembly Dark Count Rate vs. coincidence time DT DCRCOINC = DCR1 x DCR2 x 2DT T = 20°C DT = 1.5ns DT = 10ns DT = 0.75ns DCRCOINC = 27 counts/s mm2
b-source measurements 90Sr β source – 37kBq at 2mm distance from sensor VEX = 2V T = 5°C Dt = 0.75ns ~ 2x10-3 counts/pixel s Count rate ~0.5 counts/s mm2
Summary Strengths: Can be thinned to a few microns: low material budget Timing resolution Low power consumption Weaknesses: Radiation tolerance Geometric efficiency: surface device guard ring and electronics Opportunities: Progress in SPAD production and 3D integration technologies: many major foundries active Threats: - Cost and accessibility of 3D integration processes
Future work Current prototype: Design of new prototype: Test beam at CERN just finished: analysis of test beam results on-going Radiation hardness Design of new prototype: Larger array Improved fill factor Optimized timing Optimized power consumption
Thank you
Additional slides
Geiger-mode avalanche detectors a.k.a. Single-Photon Avalanche Diodes (SPADs), Silicon Photomultipliers 1 primary generated electron-hole pair: very large current pulse ~105 - 106 electrons Vout VBIAS > VBD SPAD Vout RQ time events
Experimental results - summary Characterization of single-layer sensors: Core supply current (at 1.8V): 8mA Breakdown voltage uniformity Dark count rate distribution Cross-talk Timing resolution Characterization of vertically integrated sensors Coincidence Dark Count Rate Measurements with 90Sr β source Test beam with protons at CERN (data analysis in due course)
Coincidence detection 1 2 3 4 5 6 7 Count rate in coincidence between two pixels in the same column Normalized rate: 𝐶 𝑅 𝑀𝑒𝑎𝑠 2∙𝐶 𝑅 1 ∙𝐶 𝑅 2 ∙∆𝑇 Cross-talk Cross-talk
Photo-Detection Efficiency Type 1: p+/nwell Type 2: pwell/niso Shallower junction: better NUV – Blue efficiency Wider depletion region: Better red-IR efficiency L. Pancheri et al., J. Selected Topics in Quantum Electron, 2015
DCR temperature dependence Devices with 43μm x 45μm active area, but different DCR Measurements from -30°C to 50°C with 10°C steps Overvoltage: VOV = 3.3V
Breakdown probability (Pb) IR light: uniform generation, Pb measured for a single photoelectron Particles generate N primary electrons: PbN = 1 – (1-Pb)N Example: single electron Pb = 30% 10 electrons Pb10 = 97% L. Pancheri et al., J. Selected Topics in Quantum Electron, 2015
VBD extraction method VREF VBD extraction from I-V curves: not possible VBD extracted from the dark count rate vs. voltage curve L. Pancheri et al., Proc. IEEE ICMTS, 2014
Dark Count Rate vs. bias Active area: 43μm x 45μm
Effect of crosstalk in DCR distribution Thickness 280 µm Thickness 50 µm Median DCR increase of 70% for 280µm sample and 400% for 50µm sample
Timing resolution IR laser (780nm) 50ps FWHM Diffuser Sensor VEX = 1V 208ps FWHM Diffuser Sensor Coincidence output Timing histogram between laser trigger and sensor coincidence output N.B. Design not optimized for timing 2 pixels enabled