Circuits and Interconnects In Aggressively Scaled CMOS 9/6/2018 Circuits and Interconnects In Aggressively Scaled CMOS Mark Horowitz Computer Systems Laboratory Stanford University horowitz@stanford.edu VLSI Scaling

Device Scaling In digital CMOS design: Only two circuit forms matter (maybe three) Static CMOS, and Dynamic CMOS These forms are used because: They don’t demand much from devices So they work with crummy transistors Robust, especially static circuits VLSI Scaling

FO4 Inverter Delay Under Scaling Device performance will scale FO4 delay has been linear with tech Approximately 0.36 nS/mm*Ldrawn at TT (0.5nS/mm under worst-case conditions) Easy to predict gate performance We can measure them Labs have built 0.04mm devices Key issue is voltage scaling 1 3 5 7 0.5 1.5 2 FO4 delay (nS) Feature size (mm) 0.36 * Ldrawn VLSI Scaling

Circuit Power Is very much tied to voltage scaling If the power supply scales with technology For a fixed complexity circuit Power scales down as a^3 if you run as same frequency Power scales down as a^2 if you run it 1/ a times faster Power scaling is a problem because Freq has been scaling at faster than 1/ a Complexity of machine has been growing This will continue to be an issue in future chips Remember scaling the technology makes a chip lower power! VLSI Scaling

Voltage Scaling Circuits performance depends on the Vdd to Vth ratio Ideally both should scale together If Vth scales leakage scales If Vth does not scale, gates get slower, or Vdd can’t scale as fast and power goes up Leakage is easier to deal with than power, transistors will leak Tech 0.8 0.5 0.35 0.25 0.18 0.13 0.10 Vdd 5 3.3 2.5 1.8 1.3 1.0 Vth ?? VLSI Scaling

Scaling Global Wires R gets quite a bit worse with scaling; C basically constant 0.1 0.2 0.3 0.4 0.25 0.18 0.13 0.07 0.05 0.035 Kohms Technology Ldrawn (um) Semi-global wire resistance, 1mm long Aggressive scaling Conservative scaling 0.2 0.4 0.6 0.25 0.18 0.13 0.1 0.07 0.05 0.035 pF Technology Ldrawn (um) Semi-global wire capacitance, 1mm long Aggressive scaling Conservative scaling VLSI Scaling

Scaling Module Wires R is basically constant, and C falls linearly with scaling 0.1 0.2 0.3 0.4 0.25 0.18 0.13 0.07 0.05 0.035 Kohms Technology Ldrawn (um) Semi-global wire resistance, scaled length Aggressive scaling Conservative scaling 0.2 0.4 0.6 0.25 0.18 0.13 0.1 0.07 0.05 0.035 pF Technology Ldrawn (um) Semi-global wire capacitance, scaled length Aggressive scaling Conservative scaling VLSI Scaling

Architecture Scaling Plot of IPC Compiler + IPC 1.5x / generation What next? Wider machines Threads Speculation Guess answers to create parallelism Have high wire costs Won’t be easy VLSI Scaling

Clock Frequency Most of performance comes from clock scaling Clock frequency double each generation Two factors contribute: technology (1.4x/gen), circuit design VLSI Scaling

Gates Per Clock Clock speed has been scaling faster than base technology Number of FO4 delays in a cycle has been falling Number of gates decrease 1.4x each generation Caused by: Faster circuit families (dynamic logic) Better optimization Approaching a limit: <16 FO4 is hard < 8 FO4 is very hard VLSI Scaling