PS Transverse Dampers Progress report on Firmware PS TFB PS Transverse Dampers Progress report on Firmware Aknowledgments: Fesa class: Ylenia BRISCHETTO Andy BUTTERWORTH Michael JAUSSI Ioan KOZSAR Visual Elite: Gregoire HAGMANN José NOIRJEAN Damien PERRELET Betatron phase versus tune value PS machine simulated data: Guido STERBINI Alfred BLAS LIU-PS 2015, 23 June 2015

PS Transverse Dampers Progress report on Firmware PS TFB PS Transverse Dampers Progress report on Firmware Executive summary The hardware tests will start on the 24th June 2015 This means testing: 93 registers (=> functions) 6 multiplexed observation channels (oasis) to test 18 input/output on front panel Ready for use in the PS: mid-August Alfred BLAS LIU-PS 2015, 23 June 2015

PS Transverse Dampers Progress report on Firmware PS TFB PS Transverse Dampers Progress report on Firmware History 12-01-2015 : start of the firmware development (at part time – 50 %) 03-04-2015 : VHDL coding completed using Visual Elite and Cheburashka. 07-04-2015 : Frequency offset function generator added to the blow-up circuit issues encountered with Cheburashka and Gena 18-05-2015 : VHDL compiled by Quartus to create the FPGA programming file. result : design cannot fit the chip (113% of ALUs, 53% of logic cells) 25-05-2015 : VHDL simplified => fits inside the chip but max clock frequency too low (90 MHz) 05-06-2015 : Max clock frequency = 136 MHz after staggering of heavy arithmetic blocs 21-06-2015 : deployment of the Fesa class and timing into the lab test crate (about 2 weeks lost due to priority for Isolde). Observation system not yet ready Alfred BLAS LIU-PS 2015, 23 June 2015

PS Transverse Dampers low-level Hardware PS TFB PS Transverse Dampers low-level Hardware C0 PS h1 PS h200 Tune value CVORB TFB loop Gain CVORB D PU 98 D PU 02 Tune excitation Blow-up excitation Output to power amplifiers Tune excitation OASIS PS h200 clock OASIS PU D 98 OASIS PU D 02 OASIS PS h1 OASIS Blow-up excitation OASIS Betatron phase CVORB BLU harm. Offset CVORB Alfred BLAS LIU-PS 2015, 23 June 2015

PS Transverse Dampers Synoptic PS TFB PS Transverse Dampers Synoptic Alfred BLAS LIU-PS 2015, 23 June 2015

PS Transverse Dampers Synoptic PS TFB PS Transverse Dampers Synoptic 9 independent sinewave oscillators are available to excite the beam. Harmonic, amplitude and initial phase are set individually. This excitation can be applied to all the beam or within 1 up to 3 bunch-synchronous-windows Alfred BLAS LIU-PS 2015, 23 June 2015

PS Transverse Dampers Cheburashka PS TFB PS Transverse Dampers Cheburashka List of registers and register-blocks Register’s details: address, bits’ description, weighting factors, encoding type, access (r, rw, rwm, auto-clear) 58 registers of 16 bits 34 registers of 32 b 1 register of 64 bits Access to 4 SRAM channels of 4 MBytes Alfred BLAS LIU-PS 2015, 23 June 2015

PS Transverse Dampers Firmware specifications PS TFB PS Transverse Dampers Firmware specifications Main new specifications: Sophisticated internal excitation-source with bunch gating. Loop gain control (FG and knob) Tune excitation and blow-up sources treated centrally with gating capabilities to avoid conflicts between functions Extensive monitoring capabilities along the cycle covering all internal signals, timing and status flags. Upgraded automatic delay (less prone to a 1 Tck jitter) Upgraded C-train soft-timing with 10 us jitter instead of 1 ms Firmware design using the standard “visual elite”, “gena” and “cheburaska” tools Alfred BLAS LIU-PS 2015, 23 June 2015

PS Transverse Dampers Conclusion PS TFB PS Transverse Dampers Conclusion Conclusion: The hardware tests are starting now. At the same time, the knobs creation (Inca) will be launched for machine operation The availability for operation is expected mid August (taking into account holidays and part time involvement) The acquisition part of the Fesa class is still requiring some effort. Personal experience: Using the FPGA programming tools defined as a standard in the section: Visual Elite -> Cheburashka -> Gena -> Quartus + archiving (RCS + SVN) instead of Quartus on its own, represents a time consuming “investment” especially for a non regular designer. Alfred BLAS LIU-PS 2015, 23 June 2015