Second generation Front-end chip for H-Cal SiPM readout : SPIROC M. Bouchel, S. Callier, F. Dulucq, J. Fleury, C. de La Taille, G. Martin-Chassard, L. Raux LAL Orsay IN2P3-CNRS – Université Paris-Sud – B.P. 34 – 91898 Orsay cedex – France Réunion EUDET – CERN – jeudi 12 juillet 2007

Second generation chip for SiPM : SPIROC A-HCAL read out Silicon PM detector 36-channel prototype Compatible with new DAQ Many SKIROC, HARDROC, and MAROC features re-used Technology : AMS SiGe 0.35μm technology surface :32mm² (4.2mm × 7.2mm) power supply: 5V/3.5V Consumption 25μW per channel (in power pulsing mode Package: CQFP240 Prototype cost: 30k Euros submitted on 11th june 2007 Delivery expected in September 2007

SPIROC main features 36-channel readout chip Internal input 8-bit DAC (0-5V) for SiPM gain adjustment Energy measurement : 2 gains / 12 bit ADC 1 pe  2000 pe Variable shaping time from 50ns to 100ns pe/noise ratio : 11 Time measurement : 1 TDC (12 bits) step~100 ps pe/noise ratio on trigger channel : 24 Fast shaper : ~15ns Auto-Trigger on ½ pe Analog memory for time and charge measurement : depth 16 Low consumption : ~25µW per channel (in power pulsing mode) Calibration injection capacitance Embedded band gap for voltage references and DAC for trigger threshold Compatible with physic prototype DAQ Serial analogue output External “force trigger” 12-bit Bunch Crossing ID SRAM with data formatting 2 x 2kbytes = 4kbytes Output & control with daisy-chain Probe bus for debug : 939 probe points Very versatile: 703 slow control parameters

SPIROC Test board Maroc test board Commercial 12-bit ADC ALTERA Cyclone GPIB port 64ch PM socket USB port ASIC Programmable by JTAG Maroc test board

SPIROC Test board Similar to MAROC, HARDROC, SKIROC test boards Schematic in progress ALTERA Cyclone EP1C6 is used USB or GPIB port Interface for SiPM DAQ interface?

Schedule Prototype submission : 11th june 2007 Test board schematic in progress and should be completed end of July Expected chips and test board delivery : End of September 2007 Test board debug at LAL in first half of October 2007 Test board with chips available second half of October 2007 SPIROC Characterization : Desy Group and LAL- End of Year

Conclusion SPIROC designed for SiPM A-HCAL : second generation ASIC Many SKIROC, HARDROC, and MAROC features re-used for SPIROC : power pulsing, bandgap, daisy chain mechanism, etc. New features embedded : Time measurement, low consumption input DAC, etc. Compatible with new DAQ Submission in june 2007 and first prototype expected in September 2007

Backup slides

Block scheme of SPIROC SRAM HCAL SLAB Analog mem. 36-channel 12-bit Bunch crossing Ch. 0 Ch. 1 Analog channel Analog mem. 36-channel 12-bit Wilkinson ADC for charge and time measurement Ch. 35 12-bit counter Time digital mem. Event builder Memory pointer Trigger control Main SRAM Com module HCAL SLAB

SPIROC : One channel schematic 50 -100ns 50-100ns Gain selection 4-bit threshold adjustment 10-bit DAC 15ns DAC output HOLD Slow Shaper Fast Shaper Time measurement Charge measurement TDC ramp 300ns/5 µs 12-bit Wilkinson ADC Trigger Depth 16 Common to the 36 channels 8-bit DAC 0-5V Low gain Preamplifier High gain Preamplifier Analog memory 15pF 1.5pF 0.1pF-1.5pF Conversion 80 µs READ Variable delay IN Discri Gain Flag TDC IN test

SPIROC : Photoelectron response simulation Simulation obtained with SiPM gain = 106 _ 1 pe = 160 fC High gain Preamplifier response Low gain Preamplifier response Fast shaper Tp=15ns Noise/pe ratio = 25 120mV/pe High gain Slow shaper 10mV/pe Tp=50ns Noise/pe ratio = 11 Low gain Slow shaper Tp=50ns 1mV/pe Noise/pe ratio = 3

Acquisition Channel 0 Conversion ADC + readout Ecriture RAM Channel 1 ValidHoldAnalogb 16 RazRangN Chipsat 16 ReadMesureb 16 Acquisition NoTrig gain Trigger discri Output Wilkinson ADC Discri output ExtSigmaTM (OR36) StartAcqt SlowClock Hit channel register 16 x 36 x 1 bits TM (Discri trigger) 36 BCID 16 x 8 bits Channel 0 gain Trigger discri Output Wilkinson ADC Discri output Conversion ADC + Ecriture RAM StartConvDAQb 36 ValGain (low gain or high Gain) TransmitOn readout RamFull OutSerie 36 EndReadOut EndRamp (Discri ADC Wilkinson) StartReadOut FlagTDC Rstb Channel 1 Clk40MHz ..… ADC ramp Startrampb (wilkinson ramp) RAM OR36 … StartRampTDC TDC ramp ChipID Chip ID register 8 bits 8 ValDimGray DAQ ASIC ValDimGray 12 bits 12

Channel Discriminator 50ns Start_ramp_TDC 16 16 Ramp signal 50ns ValidHoldAnalogb TDC Ramp Channel Digital Block Discri signal Discri SCA T 50ns Hold 16 16 50ns RazRangNb 16 Channel Discriminator Shaper high gain SCA Q HG Hold 16 16 50ns Shaper low gain SCA Q LG Hold 16 OR36 50ns OR36

Gain and dark rate uniformity correction The input DACs allow to adjust HV channel by channel via slow control on the 8000 SiPM of the detector +HV 100kΩ 100nF 8-bit DAC SiPM Preamp input 50Ω ASIC 100nF High voltage on the cable shielding

SPIROC : RAM Mapping Time Measurement 1168 15 ..................... 16 ..................... 16 16x36 Time stamp (BCID) Chip ID (8 bits) 0 0 0 0 0 0 7 Time stamp (12 bits) TDC measurement (12 bits) ADC measurement (12 bits) Gain (1 bit) Hit (1 bit) Charge Measurement

SPIROC : Acquisition mode Store up to 16 events in RAM Stop acquisition when ram_full signal asserted Common collector bus for ram_full signal 36

SPIROC : Readout mode Based on daisy chain mechanism initiated by DAQ Possibility to bypass a chip by slow control One data line activated by each chip sequentially Readout rate few MHz to minimize power dissipation With 500 pF bus capacitance, power dissipation is ~10µW/chip i=CdV/dt = 1 mA => 1 mW for up to 100 chips on bus Readout time max (ram full) 20kbits x 1 µs = 20 ms/chip

SPIROC running modes Acquisition A/D conversion DAQ When an event occur : Charge is stored in analogue memory Time is stored in digital (coarse) and analogue (fine) memory Trigger is automatically rearmed at next coarse time flag (bunch crossing ID) Depht of memory is 16 The data (charge and time) stored in the analogue memory are sequentially converted in digital and stored in a SRAM. An event in RAM is : The coarse time The fine time The charge The shaper gain The status of the trigger The events stored in the RAM are outputted through a serial link when the chip gets the token allowing the data transmission. When the transmission is done, the token is transferred to the next chip. 256 chips can be read out through one serial link

Time considerations A/D conv. DAQ IDLE MODE 99% duty cycle Time between two trains: 200ms (5 Hz) time Time between two bunch crossing: 337 ns Train length 2820 bunch X (950 us) analog detectors only Acquisition A/D conv. DAQ IDLE MODE 1ms (.5%) .5ms (.25%) .5ms (.25%) 199ms (99%) 99% duty cycle 1% duty cycle

First generation chip for SiPM 18-channel 8-bit DAC (0-5V) 18-channel front-end readout : Variable gain charge preamplifier (0.67 to 10 V/pC) Variable tine constant CRRC2 shaper (12 to 180 ns) Track and hold  1 multiplexed output Power consumption : ~200mW (supply : 0-5V) Technology : AMS 0.8 m CMOS Chip area : ~10mm² Package : QFP-100

First generation chip for SiPM Single photoelectron spectra Measured by LAL group at Orsay M.Groll and A. Karakash DESY / MEPhI

FLC_SIPM AHCAL TCMT 120 cm 90 cm FLC_SIPM has been designed to read out the CALICE AHCAL physics prototype It is also used in the TCMT read out ECAL beam

Tile HCAL testbeam prototype From Felix Sefkow’s talk 1 cubic metre 38 layers, 2cm steel plates 8000 tiles with SiPMs Electronics based on CALICE ECAL design, common back-end and DAQ ASICs: LAL Boards: DESY DAQ: UK DESY DESY, Hamburg U, ITEP, MEPHI, LPI (Moscow) Northern Illinois LAL, Orsay Prague UK groups Tile sizes optimized for cost reasons

Gain and dark rate uniformity correction SiPM gain varies with the high voltage value  DAC to adjust gain CHANNEL BY CHANNEL from M.Danilov ITEP, Moscow

Channel architecture for SiPM readout 40kΩ 100MΩ 0.1pF ASIC 2.4pF 8-bit DAC 0-5V 0.2pF 1.2pF 0.4pF 0.6pF 0.8pF 0.3pF in 12kΩ 4kΩ 24pF 10pF Rin = 10kΩ 50Ω 12pF 8pF 4pF 2pF 1pF 100nF 6pF 3pF Charge Preamplifier : Low noise : 1300e- @40ns Variable gain : 4bits : 0.67 to 10 V/pC CR-RC² Shaper : Variable time constant : 4 bits (12 to 180ns) 12ns  photoelectron measurement (calibration mode) 180ns  Mip measurement (physic mode) compatibility with ECAL read-out

MIP and photo-electron responses Physics mode : Cf=0.4pF- t=180ns - Rin ON 1 MIP = 16 p.e. injected Vout = 23 mV @ tp = 160 ns SLOW SHAPING FOR TRIGGER LATENCY Calibration mode : Cf=0.2pF - t=12ns - Rin OFF 1 SPE = 0.16pC injected (0.6mV in 270pF) Vout = 11 mV @ tp = 35 ns

Linearity measurement (physics mode) Voltage swing : ~2.1V Dynamic Range: 80 MIPs Linearity: <1% 0.5% -0.5%

Cross-talk measurement Capacitive coupling contribution Non-Direct neighbouring channel x100 Channel-to-Channel cross-talk : ~ 1-2‰ :negligible 2 contributions : Capacitive coupling between neighboring channels Long distance crosstalk in all channels (comes from a reference voltage) Direct neighbouring channel x100 Sampling time Long Distance cross-talk contribution Set-up: Cf=0.4pF, t=180ns

FLC_SIPM results Physics results on such high number of channel are coming up So far : Noise as expected Coherent noise very low Dynamic range as expected With russian SiPM With MPPC Tohru Takeshita & al Felix Sefkow & al

Technical prototype architecture From Felix Sefkow’s talk ~ 2000 tiles/layer LDA (Module concentrator, Optical link) Very similar to SiW ECAL Following CALICE / EUDET DAQ concept SPIROC 2nd gen ASIC incl ADC DIF (Layer Concentrator, Clock, control, Configuration) 2.2m With 40 µW / ch Temp gradient 0.3 K / 2m Layer units (assembly) subdivided into smaller PCBs HBUs:Typically 12*12 tiles, 4 ASICs

Integrated layer design From Felix Sefkow’s talk Sector wall Reflector Foil 100µm Polyimide Foil PCB 800µm Bolt with inner M3 thread welded to bottom plate MGPD Tile 3mm HBU Interface 500µm gap Bottom Plate 600µm ASIC TQFP-100 1mm high Top Plate 600µm steel Component Area: 900µm high HBU height: 6.1mm (4.9mm without covers => absorber) Absorber Plates (steel) Spacer 1.7mm fixing DESY integrated

Introduction : EUDET module The module are not foreseen to be fully equipped with detector The point is to validate feasability and industrialisation One layer for feasability and one tower for physics DHCAL (RPCs) ECAL (Si PIN diodes) AHCAL (Sci w SiPM)