Subthreshold Voltage High-k CMOS Devices Have Lowest Energy and High Process Tolerance Murali Dharan Vishwani Agrawal ICIT-SSST 20113/14/20111

Outline Motivation Background Comparison between bulk and high-k MOSFETs Sub-threshold voltage operation Methodology  Measurement of critical path delay  Energy measurement Results  Comparison between bulk and high-k technologies Process Variations  Comparison of critical path delays between bulk and high-k  Comparison of average energy/cycle between bulk and high-k Conclusion References ICIT-SSST 20113/14/20112

Motivation Growing concern for increased power and energy dissipation due to excessive leakage with the scaling down of transistors in the sub 90 nm region.  Comparing the effects of voltage scaling on bulk and high-k technologies and analyzing the circuit operations in the sub-threshold region of transistors. Reduced feature sizes of transistors can cause an increase in process variations hence causing deviations from ideal power and energy values.  Studying the effects of parametric process variations like threshold parameter (vth0), mobility (μ 0 ), oxide thickness (t oxe ) etc. on bulk and high-k technologies. 3/14/2011ICIT-SSST 20113

Background P total = P static + P dynamic  P dynamic = Power dissipated during switching of transistors  P static = Power dissipated due to leakage current Scaling down of transistors has caused a reduction in dynamic energy/cycle due to reduced load capacitances. Increase in static energy/cycle due to higher leakage current. Supply Voltage V dd has the strongest influence on components of power and energy [1].  P total = V dd x I dd 3/14/20114 ICIT-SSST 2011

Comparison between bulk and high-k MOSFETS Bulk MOSFETs have polysilicon gates and SiO 2 as gate oxide. High-k MOSFETs have metal gates and hafnium or zirconium compounds as gate oxide. Problem of e - tunneling through gate oxide as transistors were scaled down causing unreliability. High-k transistors cut down tunneling, and hence reduced power dissipated due to leakage. 3/14/20115 High-k MOSFET Design [2] Bulk MOSFET Design [2] ICIT-SSST 2011

Sub-threshold voltage operation Dynamic Voltage Scaling has shown that circuits are more energy efficient in sub-threshold regions [3].  Energy savings on the order of 9X can be obtained when compared to normal circuit operations. Studies of dual voltage design in the sub-threshold region have shown both energy and speed advantages [4].  When speed is a criteria, circuit is operated at normal operating voltage.  When energy efficiency is a criteria, circuit can be operated at sub- threshold voltage. Sub-threshold voltage operations have shown advantage in extending the battery life of portable electronics [5]. ICIT-SSST /14/20116

Measurement of critical path delay ICIT-SSST Delay 1 Delay 2 3/14/20117

Energy measurement T d = delay 1 (since, delay 1 > delay 2) 100 random vectors were applied with (T d T d ) time interval between each vector. Average current I avg drawn by the circuit was measured. Total Energy/cycle was calculated for each voltage.  E = V dd x I avg x T d ICIT-SSST 20113/14/20118

Comparison between 45 nm bulk and high-k technologies ICIT-SSST 2011 Simulated performance of 32 bit ripple carry adder in 45 nm bulk technology. Simulated performance of 32 bit ripple carry adder in 45 nm high-k technology. Voltage (V) Current x (A) Power x10 -6 (W) Delay x (s) Energy x (J) Voltage (V) Current x (A) Power x (W) Delay x (s) Energy x (J) /14/20119

Energy per cycle vs. V dd ICIT-SSST 20113/14/201110

Process variations Varied the vth0 parameter by 5 % in the PTM 5 model files of 45 nm bulk and high-k technology. 30 random samples using Monte Carlo Analysis were simulated at 0.3 V and 0.9 V for both technologies. Mean and standard deviation (σ) of critical path delays was calculated. Normalized Energy/cycle (%) = [(E ✭ - E) x 100]/ E ✭  Where E = Energy/cycle for the sample and E ✭ = Ideal Energy/cycle for that voltage operation. ICIT-SSST 20113/14/201111

Technology Mean delay x (s) Standard deviation (σ ) x10 -9 (s) Clock period x (s) (Mean + 3 σ) 45 nm bulk nm high k ICIT-SSST 2011 Critical path delays of 30 samples of 32 bit ripple carry adder circuit operating at 0.3 V designed in 45 nm bulk and high-k technologies. Technology Supply Voltage Average Energy/cycleClock period Without process variation With process variation Without Process Variation With Process variation 45 nm high-k0.9 V109 fJ113fJ0.47 ns0.516 ns 45 nm high-k0.3 V1.22 fJ1.53fJ3.71ns6.25 ns 45 nm bulk0.3 V2.19 fJ3.59 fJ137 ns338 ns Comparison of average energy/cycle and clock period for different operating voltages and technologies with and without process variation. 3/14/201112

Process variation effect on energy per cycle (%) for 30 samples of the circuit implemented in 45 nm bulk and high-k technologies and operating with 0.3 V supply (closer to x-axis is better). ICIT-SSST 20113/14/201113

Process variation effect on energy per cycle for 30 samples of the circuit designed in 45 nm high-k technology for 0.9V and 0.3V operations. ICIT-SSST 20113/14/201114

Conclusion Minimum energy per cycle for high-k technology is 40 % lower compared to bulk technology. Circuits designed in high-k operate at 250 MHz at minimum energy point is while for bulk circuits operate at just above 7 MHz. Results show that high-k technology is more resilient to process variations compared to bulk technology.  Average energy/cycle deviation for high-k is % from the ideal value.  Average energy/cycle deviation for bulk is % from the ideal value. Even with process variations in high-k technology, circuits operating at 0.3 V are more energy efficient when compared to operations at 0.9 V. ICIT-SSST /14/201115

References 1.J. D. Meindl, and R. M. Swanson, “Potential Improvements in Power Speed Performance of Digital Circuits, Potential Improvements in Power Speed Performance of Digital Circuits,” Proc. IEEE, vol. 59, no. 5, pp. 815– 816, May M. T. Bohr, R. S. Chau, T. Ghani, and K. Mistry, “The High-k Solution,” IEEE Spectrum, vol. 44, no. 10, pp , B. H. Calhoun, and A. Chandrakasan, “Ultra-Dynamic Voltage Scaling Using Sub-Threshold Operation and Local Voltage Dithering in 90nm CMOS,” Proc. IEEE International Solid-State Circuits Conference, pp , Feb K. Kim, and V. D. Agrawal, “True Minimum Energy Design Using Dual Below-Threshold Supply Voltages,” in Proc. 24th International Conference on VLSI Design, Jan M. Kulkarni, and V. D. Agrawal, “Energy Source Lifetime Optimization for a Digital System through Power Management,” Proc. 43 rd Southeastern Symposium on System Theory, March PTM website, Arizona State University, ICIT-SSST 20113/14/201116

Thank You!!! ICIT-SSST 20113/14/201117