Lab 5 – Interrupts vs Polling MPC8360 Micro Controllers 371-1-2403 Lab 5 – Interrupts vs Polling Fall , 2010

Interrupts Interrupts in the MPC8360 Interrupts vs Polling

Interrupt Flow Interrupt save/restore register - SSR0 0x10C Main Program …. 0x100 xor r3,r3,r3 0x104 r4,r4,r4 0x108 add r3,r3,r5 0x10C or r3,r4,r5 0x110 and r3,r7,r6 Interrupt Handler 0x500 add r4,r5,r3 0x504 sub r7,r4,r2 0x508 lwz r3,0(r7) … 0x570 rfi PC PC PC PC PC PC PC PC PC save/restore register - SSR0 0x10C save/restore register - SSR1 MSR

Interrupt Handler What happens to the original value of the registers overwritten by the Interrupt handler ? What Happens when we get an Interrupt inside the Interrupt handler ? Interrupt Handler 0x500 add r4,r5,r3 0x504 sub r7,r4,r2 0x508 lwz r3,0(r7) … 0x570 rfi

Interrupt Handler – General Structure 0x500 Disable Interrupts 0x504 Push Registers … 0x570 Pop Registers 0x574 Enable Interrupts 0x578 rfi

Vector Offset Interrupt Type Vector Offset (hex) Exception Conditions Reserved 00000 ---- System reset 00100 Caused by the assertion of either sreset or hreset. Machine check 00200 Caused by the assertion of the tea signal during a data bus transaction, assertion of mcp,an address or data parity error, or an instruction or data cache parity error. DSI 00300 Determined by the bit settings in the DSISR. ISI 00400 Caused when an instruction fetch cannot be performed. External interrupt 00500 Caused when MSR[EE] = 1 and the int signal is asserted. Alignment 00600 Caused when the core cannot perform a memory access.

Interrupt Flow E300 Core QUICC Engine Timers Interrupt Controller QE High QE Low

QUICC Engine System Interrupt Mask Register (CIMR) Offset 0xA0 1 …. 27 28 29 30 31 UCC1 UCC2 Timer1 Timer2 Timer3 Timer4 E300 Core QUICC Engine Timers Interrupt Controller Interrupt Controller QE High QE Low The user can mask an interrupt by clearing (setting the bit to 0) the relevant bit.

System Internal Interrupt Mask Register (SIMSR_H) E300 Core Offset 0x720 1 …. 31 QE High QE Low QUICC Engine Timers Interrupt Controller Interrupt Controller QE High QE Low The user can mask an interrupt by clearing (setting the bit to 0) the relevant bit.

Machine State Register (MSR) E300 Core QUICC Engine …. 16 ….. 31 EE Timers Interrupt Controller Interrupt Controller QE High QE Low The user can mask an interrupt by clearing (setting the bit to 0) the relevant bit.

Global Timers Mode Registers (GTMDR1) Offset 0x10 7 8 9 10 11 12 13 14 15 R W SPS CE OM ORI FRR ICLK GE Reset All Zeros

Global Timers Mode Registers (GTMDR1) Offset 0x10 7 8 9 10 11 12 13 14 15 R W SPS CE OM ORI FRR ICLK GE Reset All Zeros ORI Output Reference Interrupt Enable Disable interrupt for reference reached (does not affect interrupt on capture function). 1 Enable interrupt upon reaching the reference value.

Interrupts Flow Write an interrupt handler Load the interrupt handler to the specific location. Enable the desired interrupts Unmask the desired interrupts in all the interrupt controllers Enable the external interrupt in the MSR

General Notes Make sure to bring the codes you have written in previous labs. Please READ the exercise before you start working on it !!

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