Duckhwan Kim and Saibal Mukhopadhyay On the Design of Reliable 3D-ICs Considering Charged Device Model ESD Events Duckhwan Kim and Saibal Mukhopadhyay School of Electrical and Computer Engineering, Georgia Institute of Technology 14 Min presentation Do not talk CDM_ESD, full name Charge-device Model ESD I will talk about the risk of Electrostatic discharge event during the die stacking and the overhead of ESD protectors for each TSV.

ESD risk in 3D die stacking Comb. PI PO 2D-IC Pre-charged (VCDM) Metal TSV Device ESD Comb. + TSV PI PO 3D-IC Si-bulk Si-bulk Metal Introduce the scenario of electrostatic discharge event in 3D-die stacking. After fabricating device layer on top die, aggressive wafer thinning process is required to expose TSV. During the wafer thinning, mechanical polishing is performed and it pre-charge the top die up to VCDM. In die stacking, the pre-charged charge move from top die to bottom die. Since the power network of both die is floated during the fabrication process, there is no conducting path. Therefore, all of charge should go through the silicon bulk of bottom die. To prevent the ESD stress on CMOS connected to TSV, we need place ESD protection. In 2D-IC, we already have ESD protection in external I/O Pad to protect CDM/HBM/MM ESD event from outside. In contrast to 2D-IC, we now need ESD protection in the circuit, especially next to TSV. In this timing diagram, ESD protection for TSV is embedded in combinational circuit between two sequential elements. ESD protection will change the timing & power consumption of chip after placing ESD protectors. In this paper, we analyze the overhead of ESD protection in terms of timing and power using simple RLC model We also propose the design flow of 3D-IC from logic level to p&r for low ESD overhead Device ESD protections change timing & power. Si-bulk Analyze ESD overhead RLC model Delay and power for single TSV Delay and power for logic system Ground plate ITRS 2011 roadmap

Previous CDM-ESD works Die 2 Die 1 ESD (I/O) TSV Olson et al. (2011) wire Die ESD (I/O) J. Chun et al. (2006) CDM-ESD risk in die stacking is introduced (`11 ITRS, `12 IMEC) Before we talk about ESD protection in 3D-IC, I will briefly cover previous CDM-ESD works. Since CDM-ESD was introduced in 1999, the design method of ESD protection circuit has been studied a lot. All of the study focus on CDM ESD event on I/O Pad and they suggested to place ESD protection next to I/O pad 2011, Olson study the CDM-ESD event on I/O pad in 3D-IC with wire bonding or TSV network. Since the stress of ESD is distributed to multiple dies, they suggest placing smaller ESD protection is enough to mitigate the ESD stress came from I/O pad. 2011 ITRS Interconnection report introduce CDM-ESD risk in die stacking Our paper will introduce the CDM-ESD protectors next to a TSV and focus on the CDM-ESD event in die-stacking. Since the number of TSV is larger than the number of I/O pins, the overhead of ESD protection for entire TSVs is higher than the ESD overhead for each I/O Power Die 2 Die 1 ESD (I/O) TSV S. Chen (2012) Die 2 Die 1 ESD (I/O) TSV ? Performance

Modeling of CDM-ESD Bottom die Top die CL VSS (floating) RBULK Pre-charged (VCDM*) VDD VDD ESD PDN TSV PDN CL VSS VSS (floating) RBULK Max VGS How VCDM came as 2,000V from 2D-IC The risk of CDM-ESD in 3D-IC, This is the schematic of ESD event. Top die is precharged up to VCDM in the floated power network. Please note that we mark the supposed location of ESD protectors but we simulate the ESD event without ESD protectors. After switch is closed, such as contact during the die stacking, pre-charged charge flow into the bottom die and it shows damped oscilation. Even though the settling time is less than 50ps, its peak voltage, maximum VGS for transitior connected to TSV, is about 2,000V and when VGS is more than oxide break down voltage, which is 7~10V in 130 nm process technology, the transistor is broken. Therefore, we need ESD protector at the each side of TSV since it is oscillating. Next, we focused on the impact of load cap at the TSV on the maximum VGS under given VCDM = 2000V. Since the load cap increases, it can relieve the ESD stress more therefore the maximum VGS reduces. As the load cap of TSV is composed of ESD circuit and the input capacitor of receiver, we will introduce the optimal ESD sizing later. Let’s look at Bulk contact is tied with VSS Resistor of silicon substrate Doping density, geometry of substrate Discharging path VCDM=2,000V is for 2D-IC [`11 Olson et al]

TSV model with CDM-ESD protection circuit CDM-ESD protector: resistor + double diode Single diode + vertical PNP-BJT Under the given VCDM (2,000V), Maximum VGS and IESD are constraint This figure shows the conventional CDM-ESD protection circuit. It is made up of series resistor which reduces the peak voltage and double diodes. Double diodes are composed of a single diode and a vertical BJT since BJT can handle higher current than conventional CMOS. In this paper, we assume that VCDM is constant as 2,000V following the conventional CDM-ESD guideline since there was no experimental study about VCDM in 3d-ic die stacking. Under the VCDM, Maximum VGS is constraint by V Oxide Breakdown Voltage and maximum current through the BJT is also constraint in the same manner. We model the ESD protected TSV with R and large C. We followed the reference of RLC pi model of TSV and add series resistor and large Cap to model the ESD circuit. As you can see, RLC model shows the almost same frequency response until 10GHz. RLC model of TSV with two ESD protectors

ESD overhead: single TSV For same ESD robustness: same load cap. (CTSV + CESD + CRX) Large ESD (ESD-L) + small receiver Small ESD (ESD-S) + large receiver TSV ESD Same load cap  same power consumption As we already discussed, the maximum ESD stress is constraint by the load capacitor at the TSV. Therefore, to guarantee the same ESD robustness, the load cap of TSV should be same and it means the sum of TSV cap, ESD cap, and input cap of receiver should be constant. From this condition, we can have two design options. First we can use large ESD circuit with small receiver or use small ESD circuit with large receiver. We simulate the propagation delay and power consumption of two design types. Since the total load cap is same, the power consumption at the driver and the delay across the driver should be same. However, the large receiver with small ESD circuit shows better propagation delay and consumes more power. It means that we can place the ESD circuits and receiver optimally to get low power but robust to ESD stress. Large receiver better drive strength (-18%)  more power consumption (+62%)

ESD overhead for a logic block Case study: asynchronous 3D FIFO Two diff. frequencies (fW, fR) Two diff. voltage domains 130nm process technology 8-bit data, 4-bit address Simulation framework Therefore, we could think about the simple design flow for 3D-IC under ESD event. For case study, we choose the asynchronous 3D-IC FIFO which is divided evenly into two dies. Therefore, reading and writing the data across the TSV and the delay across the TSV directly affect on the total throughput. According to Conventional 3D-IC design flow, initial design for each die does not consider the TSV. TSV overhead will be covered during the P&R as like the other interconnect wire. After TSV insertion, the throughput is reduced due to delay across the TSV and power efficiency is also reduced. ESD insertion reduce the power efficiency more and decrease the throughput. Since the small ESD with large receiver shows the better performance in terms of delay, we put small ESD with large receiver as a default. After that, to guarantee the target throughput, we did ECO placement such as buffer insertion, or buffer resizing for the driver. From the figure, although throughput improves, it still shows the low power efficiency since the power consumption increases. Therefore, the ESD protection decrease the power efficiency 16% to avoid CDM-ESD risk under the given VCDM.

ESD overhead: logic system Die 1 Die 2 TSV Die 1 Die 2 -16% Die 1 Die 2 TSV ESD Die 1 Die 2 TSV ESD Therefore, we could think about the simple design flow for 3D-IC under ESD event. For case study, we choose the asynchronous 3D-IC FIFO which is divided evenly into two dies. Therefore, reading and writing the data across the TSV and the delay across the TSV directly affect on the total throughput. According to Conventional 3D-IC design flow, initial design for each die does not consider the TSV. TSV overhead will be covered during the P&R as like the other interconnect wire. After TSV insertion, the throughput is reduced due to delay across the TSV and power efficiency is also reduced. ESD insertion reduce the power efficiency more and decrease the throughput. Since the small ESD with large receiver shows the better performance in terms of delay, we put small ESD with large receiver as a default. After that, to guarantee the target throughput, we did ECO placement such as buffer insertion, or buffer resizing for the driver. From the figure, although throughput improves, it still shows the low power efficiency since the power consumption increases. Therefore, the ESD protection decrease the power efficiency 16% to avoid CDM-ESD risk under the given VCDM. Case study: async. 3D FIFO

The impact of TSV scaling on ESD ESD-S ESD-L ESD-S ESD-L Next, we could the expect the overhead of ESD circuit in advanced TSV fabrication technology. As the TSV is scaled, the width of TSV decrease and the aspect ratio will increases. It means that the resistance of TSV increases while it will have less capacitance. Since the cap of TSV decreases, the required ESD and receiver size increases under the same ESD robustness. Therefore, the overhead of ESD increases. 20-50 5-20 1-10 20-50 5-20 1-10 Total delay and power decreases, but ESD overhead ESD increases

Conclusions ESD protector for CDM-ESD is required for TSV. Under same ESD robustness, there is a trade-off between delay (ESD-S) and power (ESD-L) ESD overhead will increase as TSV scales down. Experimental study for VCDM in 3D-IC is required.

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