TCC-48 project status report Laboratoire Leprince Ringuet LLR Polytechnique IN2P3/CNRS Project manager : P. BUSSON (LLR) Technical manager / designer : T. ROMANTEAU (LLR) R. BENETTA (CERN), schematics M. SANCHEZ (CERN), PCB design P.RUSQUART (LAL), CAO librarian

Project requirements TCC-48, constraints analysis Co-developed by LLR and CERN, LAL for CAO Trigger Concentrator Card – 48 channels (TCC-48) for ECAL / endcaps Partitioning, detector view Each endcap is subdivided in 20 degree-sector (phi 1 to 18) Each sector is split in two parts « Inner » (Eta1) » and « Outer » (Eta0) « Inner Part » is subdivided into 7 rings (eta variable ) of a maximum 4 elements (phi angle ) « Outer Part » is subdivided into 4 rings (eta variable ) of 4 elements (phi angle ) « Inner Part » has 28 trigger towers, « Outer Part » has 16 trigger towers A trigger tower is made from 1, 2, 3, 4, 5 pseudo-strip of 5 detector crystals each Partitioning, electronic material view A single TCC-48 used for « Inner » or « Outer » part, total number of 72 boards 48 optical inputs with NGK device (4x 12) on each board, 46 maximum in use 2 FPGA Virtex4, each one used for : 11 to 30 pseudo-strip inputs , computing of 16 and 12 trigger towers, for inner configuration 18 to 24 pseudo-strip inputs, computing of 8 and 8 trigger towers, for outer configuration Each FPGA must support 18 different configurations (in order to take into account the different trigger tower definitions in the sectors)

Solutions for the project TCC-48 Architecture choice Electronic constraints A TCC-48 board must : use 1 slot VME → all components in a single side Embed up to 4 SLB cards → no components below these cards Solution and associated technologies « Solution adopted → 48 deserialiser Agilent and 2 FPGA XC4LX100 Low latency deserialiser chips High power dissipation, high pin and net count, more difficulties for PCB design Solution partially validated by TCC68 project Many different clock domain (up to 32) in a single FPGA device, specific solutions are requested Architecture choices Each FPGA must be programmed with a single design (ie a single firmware, ease the maintenance problem) Must cover 18 different configurations Routing tables in ROM used to select the pseudo-strips used for each configuration Pipelined adder to maintain the temporal coherency for all configurations SRP and DCC interfaces like TCC-68, VME interface reuses code developed at CERN An architecture « Remote Download and Debug » should be supported

Design methods automation Status of PCB design Full automated hardware architecture parameters computing Parameters extracted from a XML version of the database provided from Bristol HEP group Automatically optimized to map on predefined and generic hardware architectures Generation of SystemC test bench and VHDL models from templates Content of routing tables are automatically generated No manual optimization, speed up and error free process VHDL code development Input stages for cross clock domain feature is designed, must be modified Generic hardware VHDL templates are not fully designed TCC-48 board development status (Design started at end of February 2006) New PCB and schematics symbols were developed at LAL Orsay PCB design at CERN just completed and sent for manufacturing HCAL Trigger Readout card (aka HTR) mechanics reuse High design constraints, long time and great efforts were needed to solve them (see slides below) “Bscan Card”, services card is useful to connect JTAG ports Design finished, PCB design start next week PCB design, manufacturing, component supply and card assembly made at CERN

PCB Constraints analysis Mechanics, number of board / crate Use 1 slot VME64 → almost all components are on a single side Embed up to 4 SLB cards 48 low latency deserializer 4 NGK optical receivers 48 links at 800 Mb/s No micro-vias used Impedance controlled trace 1 data link at 1,6Gb/s Small from factor card cage Consequently → front panel is full Service card in rear panel JTAG chain connectors Debug facilities 12 TCC48 per crate 25 A estimated per card DCC, CCS into the same crate 2 blocs of 300 A per crate Consequently → distributed power Use 2 sources of 3.3V Complex power scheme 1.2V, 1.5V, 1.8V, 2.5v, 3V, 3.3V, 5V

PCB Constraints analysis Density, routing capabilities Very large input data path / input shared between 2 Virtex4 devices Specific to each Virtex4 24 direct inputs of 20 bits Up to 12 outputs of 9 bits (SLB) Shared by each Virtex4 6 inputs of 20 bits Fast interconnect bus of 40 bits 32 VME interface TTC, clock, control signals High pin count for TPG function Up to 840 signals used per Virtex4 Large package BGA-1513 (40x40) Only 1 net between 2 balls pins Low space for via implantation Consequently → very high density PCB with 16 copper layers 1 signal layer between 2 power plans Signals are impedance controlled 3 types of via (blind and throw all) Low via count necessary High swapping constraints Very long time to properly route High copper thickness for power 70 m and 35 m

PCB Constraints analysis Decoupling is a concern Very large FPGA and high pin count → unprecedented decoupling complexity Decoupling capacitors for Virtex4 2 types and 4 values are necessary Up to 3 voltages must be decoupled Decoupling scheme definition Based on spreadsheet use Computed by bank Function of I/O type and number used High pin count for a Virtex4 LX100 Up to 321 pins of power supply Consequently → high constraints Up to 216 capacitors used per device 4 sizes, down to 0.5mm x 0.25mm Geographically placed No overlapping in placement 3 weeks was needed to create it Constraints Routing capability and via placement Size of capacitor to minimize area

PCB Constraints analysis Timing, reducing the clock skew Clock synchronous design / based on use of TTC system Use the LHC clock system components TTC-RX and QPLL devices 40, 80 and 160Mhz used for all FPGA 40 Mhz for all others part of system Differential clock tree (LDS and LVPECL) Same length to minimize skew Specific clock way for SLB Differential signals from ODB connector Impedance controlled Same length for all signals Main precautions in design Dedicated linear power regulators For TTC-RX and QPLL Guard ring design for QPLL All differential signals on a same layer Minimize employment of via Dedicated layers for the clock system Dedicated buffer for clock Low skew buffers on board Global clock buffer without DCM in FPGA

Project TCC48 Conclusion Co-developed by LLR and CERN, LAL for CAO One engineer (RB) at CERN retired since July 2006 Only one hardware engineer at LLR and, one PCB designer at CERN since this date Classic and robust technologies adopted for PCB design, reducing risk No micro via or low thickness material was used Minimization of the via type to reduce the number of manufacturing stage High copper thickness adopted for power distribution Early discussions with card assembly provider New discussions are planned to integrate an efficient validation test suite in production Production 2 prototypes are expected to be available and functional at CERN in September 2007 Production (72 + 8 boards) will start in 01/2008, delivery at CERN for integration expected in 04/2008

Endcaps Inner and Outer part / Trigger tower

Electronic Partitioning Summary « Outer Part » Pseudo-strip (1 - 5) 4 rings (Eta variable) 4 elements (Phi angle) 7 rings (Eta variable) « Inner Part » Trigger tower (28 - 16)