RTL Simulator for VChip Emulator

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Presentation transcript:

RTL Simulator for VChip Emulator 1999/9/21 이 재 곤

What’s VChip system? Verification tool for Full design flow download Virtual Chip Virtual Chip download Target Chip monitor & profile Host Computer Target Board

What’s VChip system? Verification tool for Full design flow Specification Architecture design Behavioral Model Behavioral Simulator RTL Model RTL Simulator Gate-Level Model Placement & Route Fabrication chip

Simulator for H/W co-simulation Conventional simulator Simulation is just a S/W operation No H/W considerations Considerations for H/W co-simulation Some mechamism for Synchronization is needed How to solve the Parallelism?

Event-driven Simulator Signal change for a node An Event consists of… node name, time, and new signal value Why Event-driven simulator? Efficiency Feedback loop

Goal H/W co-simulation with Vchip emulator Mp3 decoder data bus modelling