Digital Logic Design م . م غيث عبد الودود تقي الكلية التقنية الهندسية / بغداد dr.nasri@mtu.edu.iq Assistant Lecturer Ghaith A. Taki Ghaith.taki@gmail.com

1. Number Systems

Common Number Systems System Base Symbols Used by humans? Used in computers? Decimal 10 0, 1, … 9 Yes No Binary 2 0, 1 Octal 8 0, 1, … 7 Hexa- decimal 16 0, 1, … 9, A, B, … F

Quantities/Counting (1 of 3) Decimal Binary Octal Hexa- decimal 1 2 10 3 11 4 100 5 101 6 110 7 111 p. 33

Quantities/Counting (2 of 3) Decimal Binary Octal Hexa- decimal 8 1000 10 9 1001 11 1010 12 A 1011 13 B 1100 14 C 1101 15 D 1110 16 E 1111 17 F

Quantities/Counting (3 of 3) Decimal Binary Octal Hexa- decimal 16 10000 20 10 17 10001 21 11 18 10010 22 12 19 10011 23 13 10100 24 14 10101 25 15 10110 26 10111 27 Etc.

Conversion Among Bases The possibilities: Decimal Octal Binary Hexadecimal pp. 40-46

Quick Example 2510 = 110012 = 318 = 1916 Base

Decimal to Decimal (just for fun) Octal Binary Hexadecimal Next slide…

Weight 12510 => 5 x 100 = 5 2 x 101 = 20 1 x 102 = 100 125 Base

Binary to Decimal Decimal Octal Binary Hexadecimal

Binary to Decimal Technique Multiply each bit by 2n, where n is the “weight” of the bit The weight is the position of the bit, starting from 0 on the right Add the results

Example Bit “0” 1010112 => 1 x 20 = 1 1 x 21 = 2 0 x 22 = 0 1 x 23 = 8 0 x 24 = 0 1 x 25 = 32 4310

Octal to Decimal Decimal Octal Binary Hexadecimal

Octal to Decimal Technique Multiply each bit by 8n, where n is the “weight” of the bit The weight is the position of the bit, starting from 0 on the right Add the results

Example 7248 => 4 x 80 = 4 2 x 81 = 16 7 x 82 = 448 46810

Hexadecimal to Decimal Octal Binary Hexadecimal

Hexadecimal to Decimal Technique Multiply each bit by 16n, where n is the “weight” of the bit The weight is the position of the bit, starting from 0 on the right Add the results

Example ABC16 => C x 160 = 12 x 1 = 12 B x 161 = 11 x 16 = 176 A x 162 = 10 x 256 = 2560 274810

Decimal to Binary Decimal Octal Binary Hexadecimal

Decimal to Binary Technique Divide by two, keep track of the remainder First remainder is bit 0 (LSB, least-significant bit) Second remainder is bit 1 Etc.

Example 2 125 62 1 12510 = ?2 2 31 0 2 15 1 2 7 1 2 3 1 2 1 1 2 0 1 12510 = 11111012

Octal to Binary Decimal Octal Binary Hexadecimal

Octal to Binary Technique Convert each octal digit to a 3-bit equivalent binary representation

Example 7058 = ?2 7 0 5 111 000 101 7058 = 1110001012

Hexadecimal to Binary Decimal Octal Binary Hexadecimal

Hexadecimal to Binary Technique Convert each hexadecimal digit to a 4-bit equivalent binary representation

Example 10AF16 = ?2 1 0 A F 0001 0000 1010 1111 10AF16 = 00010000101011112

Decimal to Octal Decimal Octal Binary Hexadecimal

Decimal to Octal Technique Divide by 8 Keep track of the remainder

Example 123410 = ?8 8 1234 154 2 8 19 2 8 2 3 8 0 2 123410 = 23228

Decimal to Hexadecimal Octal Binary Hexadecimal

Decimal to Hexadecimal Technique Divide by 16 Keep track of the remainder

Example 123410 = ?16 16 1234 77 2 16 4 13 = D 0 4 123410 = 4D216

Binary to Octal Decimal Octal Binary Hexadecimal

Binary to Octal Technique Group bits in threes, starting on right Convert to octal digits

Example 10110101112 = ?8 1 011 010 111 1 3 2 7 10110101112 = 13278

Binary to Hexadecimal Decimal Octal Binary Hexadecimal

Binary to Hexadecimal Technique Group bits in fours, starting on right Convert to hexadecimal digits

Example 10101110112 = ?16 10 1011 1011 B B 10101110112 = 2BB16

Octal to Hexadecimal Decimal Octal Binary Hexadecimal

Octal to Hexadecimal Technique Use binary as an intermediary

Example 10768 = ?16 1 0 7 6 001 000 111 110 2 3 E 10768 = 23E16

Hexadecimal to Octal Decimal Octal Binary Hexadecimal

Hexadecimal to Octal Technique Use binary as an intermediary

Example 1F0C16 = ?8 1 F 0 C 0001 1111 0000 1100 1 7 4 1 4 1F0C16 = 174148

Exercise – Convert ... Decimal Binary Octal Hexa- decimal 33 1110101 703 1AF Don’t use a calculator! Skip answer Answer

Exercise – Convert … Decimal Binary Octal Hexa- decimal 33 100001 41 Answer Decimal Binary Octal Hexa- decimal 33 100001 41 21 117 1110101 165 75 451 111000011 703 1C3 431 110101111 657 1AF

Common Powers (1 of 2) Base 10 Power Preface Symbol pico p nano n 10-12 pico p 10-9 nano n 10-6 micro  10-3 milli m 103 kilo k 106 mega M 109 giga G 1012 tera T Value .000000000001 .000000001 .000001 .001 1000 1000000 1000000000 1000000000000

Common Powers (2 of 2) What is the value of “k”, “M”, and “G”? Base 2 Power Preface Symbol 210 kilo k 220 mega M 230 Giga G Value 1024 1048576 1073741824 What is the value of “k”, “M”, and “G”? In computing, particularly w.r.t. memory, the base-2 interpretation generally applies

Example In the lab… 1. Double click on My Computer 2. Right click on C: 3. Click on Properties / 230 =

Exercise – Free Space Determine the “free space” on all drives on a machine in the lab Drive Free space Bytes GB A: C: D: E: etc.

Review – multiplying powers For common bases, add powers ab  ac = ab+c 26  210 = 216 = 65,536 or… 26  210 = 64  210 = 64k

Binary Addition (1 of 2) Two 1-bit values A B A + B 1 10 “two” 1 10 “two” pp. 36-38

Binary Addition (2 of 2) Two n-bit values Add individual bits Propagate carries E.g., 1 1 10101 21 + 11001 + 25 101110 46

Multiplication (1 of 3) Decimal (just for fun) 35 x 105 175 000 35 3675 pp. 39

Multiplication (2 of 3) Binary, two 1-bit values A B A  B 1

Multiplication (3 of 3) Binary, two n-bit values As with decimal values E.g., 1110 x 1011 1110 1110 0000 1110 10011010

Fractions Decimal to decimal (just for fun) 3.14 => 4 x 10-2 = 0.04 1 x 10-1 = 0.1 3 x 100 = 3 3.14 pp. 46-50

Fractions 10.1011 => 1 x 2-4 = 0.0625 1 x 2-3 = 0.125 0 x 2-2 = 0.0 1 x 2-1 = 0.5 0 x 20 = 0.0 1 x 21 = 2.0 2.6875 pp. 46-50

Fractions Decimal to binary .14579 x 2 0.29158 x 2 0.58316 x 2 1.16632 x 2 0.33264 x 2 0.66528 x 2 1.33056 etc. 3.14579 11.001001... p. 50

Exercise – Convert ... Decimal Binary Octal Hexa- decimal 29.8 101.1101 3.07 C.82 Don’t use a calculator! Skip answer Answer

Exercise – Convert … Decimal Binary Octal Hexa- decimal 29.8 Answer Decimal Binary Octal Hexa- decimal 29.8 11101.110011… 35.63… 1D.CC… 5.8125 101.1101 5.64 5.D 3.109375 11.000111 3.07 3.1C 12.5078125 1100.10000010 14.404 C.82

Digital Systems: Logic Gates and Boolean Algebra

Objectives Perform the three basic logic operations. Describe the operation of and construct the truth tables for the AND, NAND, OR, and NOR gates, and the NOT (INVERTER) circuit. Draw timing diagrams for the various logic-circuit gates. Write the Boolean expression for the logic gates and combinations of logic gates. Implement logic circuits using basic AND, OR, and NOT gates. Appreciate the potential of Boolean algebra to simplify complex logic circuits.

Objectives (cont’d)‏ Use DeMorgan's theorems to simplify logic expressions. Use either of the universal gates (NAND or NOR) to implement a circuit represented by a Boolean expression. Explain the advantages of constructing a logic-circuit diagram using the alternate gate symbols versus the standard logic-gate symbols. Describe the concept of active-LOW and active-HIGH logic symbols. Draw and interpret the IEEE/ANSI standard logic-gate symbols.

Boolean Constants and Variables Boolean 0 and 1 do not represent actual numbers but instead represent the state, or logic level. Closed switch Open switch Yes No High Low On Off True False Logic 1 Logic 0

Three Basic Logic Operations OR AND NOT

Truth Tables A truth table is a means for describing how a logic circuit’s output depends on the logic levels present at the circuit’s inputs. 1 x B A Output Inputs A ? x B

OR Operation Boolean expression for the OR operation: x =A + B The above expression is read as “x equals A OR B” Figure 3-2

OR Gate An OR gate is a gate that has two or more inputs and whose output is equal to the OR combination of the inputs. Figure 3-3

Example 3-1 Using an OR gate in an alarm system(refer to Fg03- 04.ckt)‏

Example 3.2 Timing diagram (refer to Fg03-05.ckt)‏

AND Operation Boolean expression for the AND operation: x =A B The above expression is read as “x equals A AND B”

AND Gate An AND gate is a gate that has two or more inputs and whose output is equal to the AND product of the inputs. Figure 3-8

AND Gate An AND gate is a gate that has two or more inputs and whose output is equal to the AND product of the inputs. Figure 3-8

AND Gate An AND gate is a gate that has two or more inputs and whose output is equal to the AND product of the inputs. Figure 3-8

Timing Diagram for AND Gate

NOT Operation The NOT operation is an unary operation, taking only one input variable. Boolean expression for the NOT operation: x = A The above expression is read as “x equals the inverse of A” Also known as inversion or complementation. Can also be expressed as: A’ Figure 3-11 A

NOT Circuit Also known as inverter. Always take a single input Application:

Describing Logic Circuits Algebraically Any logic circuits can be built from the three basic building blocks: OR, AND, NOT Example 1: x = A B + C Example 2: x = (A+B)C Example 3: x = (A+B)‏ Example 4: x = ABC(A+D)‏

Examples 1,2

Examples 3

Example 4

Evaluating Logic-Circuit Outputs x = ABC(A+D) Determine the output x given A=0, B=1, C=1, D=1. Can also determine output level from a diagram

Figure 3.16

Implementing Circuits from Boolean Expressions We are not considering how to simplify the circuit in this chapter. y = AC+BC’+A’BC x = AB+B’C x=(A+B)(B’+C)‏

Figure 3.17

Figure 3.18

NOR Gate Boolean expression for the NOR operation: x = A + B Figure 3-20: timing diagram

Figure 3.20

NAND Gate Boolean expression for the NAND operation: x = A B Figure 3-23: timing diagram

Figure 3.23

Boolean Theorems (Single-Variable)‏ x* 0 =0 x* 1 =x x*x=x x*x’=0 x+0=x x+1=1 x+x=x x+x’=1

Boolean Theorems (Multivariable)‏ x+y = y+x x*y = y*x x+(y+z) = (x+y)+z=x+y+z x(yz)=(xy)z=xyz x(y+z)=xy+xz (w+x)(y+z)=wy+xy+wz+xz x+xy=x x+x’y=x+y x’+xy=x’+y

DeMorgan’s Theorems (x+y)’=x’y’ Implications and alternative symbol for NOR function (Figure 3-26)‏ (xy)’=x’+y’ Implications and alternative symbol for NAND function (Figure 3-27)‏ Example 3-17: Figure 3-28 Extension to N variables

Figure 3.26

Figure 3.27

Universality of NAND Gates

Universality of NOR Gates

Available ICs

Alternate Logic Symbols Step 1: Invert each input and output of the standard symbol Change the operation symbol from AND to OR, or from OR to AND. Examples: AND, OR, NAND, NOR, INV

Alternate Logic-Gate Representation

Logic Symbol Interpretation When an input or output on a logic circuit symbol has no bubble on it, that line is said to be active-HIGH. Otherwise the line is said to be active-LOW.

Figure 3.34

Figure 3.35

Which Gate Representation to Use? If the circuit is being used to cause some action when output goes to the 1 state, then use active-HIGH representation. If the circuit is being used to cause some action when output goes to the 0 state, then use active-LOW representation. Bubble placement: choose gate symbols so that bubble outputs are connected to bubble inputs, and vice versa.

Figure 3.36

IEEE Standard Logic Symbols NOT AND OR NAND NOR 1 A x A & x B A ≧1 x A & x A ≧1 x B B B

Combinational Logic Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of input variables, logic gates, and output variables.

4-2. Analysis procedure To obtain the output Boolean functions from a logic diagram, proceed as follows: Label all gate outputs that are a function of input variables with arbitrary symbols. Determine the Boolean functions for each gate output. Label the gates that are a function of input variables and previously labeled gates with other arbitrary symbols. Find the Boolean functions for these gates.

4-2. Analysis procedure Repeat the process outlined in step 2 until the outputs of the circuit are obtained. By repeated substitution of previously defined functions, obtain the output Boolean functions in terms of input variables.

Example F2 = AB + AC + BC; T1 = A + B + C; T2 = ABC; T3 = F2’T1; F1 = T3 + T2 F1 = T3 + T2 = F2’T1 + ABC = A’BC’ + A’B’C + AB’C’ + ABC

Derive truth table from logic diagram We can derive the truth table in Table 4-1 by using the circuit of Fig.4-2.

4-3. Design procedure Table4-2 is a Code-Conversion example, first, we can list the relation of the BCD and Excess-3 codes in the truth table.

Karnaugh map For each symbol of the Excess-3 code, we use 1’s to draw the map for simplifying Boolean function.

Circuit implementation z = D’; y = CD + C’D’ = CD + (C + D)’ x = B’C + B’D + BC’D’ = B’(C + D) + B(C + D)’ w = A + BC + BD = A + B(C + D)

4-4. Binary Adder-Subtractor A combinational circuit that performs the addition of two bits is called a half adder. The truth table for the half adder is listed below: S = x’y + xy’ C = xy S: Sum C: Carry

Implementation of Half-Adder

Full-Adder One that performs the addition of three bits(two significant bits and a previous carry) is a full adder.

Simplified Expressions C S = x’y’z + x’yz’ + xy’z’ + xyz C = xy + xz + yz

Full adder implemented in SOP

Another implementation Full-adder can also implemented with two half adders and one OR gate (Carry Look-Ahead adder). S = z ⊕ (x ⊕ y) = z’(xy’ + x’y) + z(xy’ + x’y)’ = xy’z’ + x’yz’ + xyz + x’y’z C = z(xy’ + x’y) + xy = xy’z + x’yz + xy

Binary adder This is also called Ripple Carry Adder ,because of the construction with full adders are connected in cascade.

Carry Propagation Fig.4-9 causes a unstable factor on carry bit, and produces a longest propagation delay. The signal from Ci to the output carry Ci+1, propagates through an AND and OR gates, so, for an n-bit RCA, there are 2n gate levels for the carry to propagate from input to output.

Carry Propagation Because the propagation delay will affect the output signals on different time, so the signals are given enough time to get the precise and stable outputs. The most widely used technique employs the principle of carry look-ahead to improve the speed of the algorithm.

Boolean functions Pi = Ai ⊕ Bi steady state value Gi = AiBi steady state value Output sum and carry Si = Pi ⊕ Ci Ci+1 = Gi + PiCi Gi : carry generate Pi : carry propagate C0 = input carry C1 = G0 + P0C0 C2 = G1 + P1C1 = G1 + P1G0 + P1P0C0 C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0 C3 does not have to wait for C2 and C1 to propagate.

Logic diagram of carry look-ahead generator C3 is propagated at the same time as C2 and C1.

4-bit adder with carry lookahead Delay time of n-bit CLAA = XOR + (AND + OR) + XOR

Binary subtractor M = 1subtractor ; M = 0adder

Overflow It is worth noting Fig.4-13 that binary numbers in the signed-complement system are added and subtracted by the same basic addition and subtraction rules as unsigned numbers. Overflow is a problem in digital computers because the number of bits that hold the number is finite and a result that contains n+1 bits cannot be accommodated.

Overflow on signed and unsigned When two unsigned numbers are added, an overflow is detected from the end carry out of the MSB position. When two signed numbers are added, the sign bit is treated as part of the number and the end carry does not indicate an overflow. An overflow cann’t occur after an addition if one number is positive and the other is negative. An overflow may occur if the two numbers added are both positive or both negative.

4-5 Decimal adder BCD adder can’t exceed 9 on each input digit. K is the carry.

Rules of BCD adder When the binary sum is greater than 1001, we obtain a non-valid BCD representation. The addition of binary 6(0110) to the binary sum converts it to the correct BCD representation and also produces an output carry as required. To distinguish them from binary 1000 and 1001, which also have a 1 in position Z8, we specify further that either Z4 or Z2 must have a 1. C = K + Z8Z4 + Z8Z2

Implementation of BCD adder A decimal parallel adder that adds n decimal digits needs n BCD adder stages. The output carry from one stage must be connected to the input carry of the next higher-order stage. If =1 0110

4-6. Binary multiplier Usually there are more bits in the partial products and it is necessary to use full adders to produce the sum of the partial products. And

4-bit by 3-bit binary multiplier For J multiplier bits and K multiplicand bits we need (J X K) AND gates and (J − 1) K-bit adders to produce a product of J+K bits. K=4 and J=3, we need 12 AND gates and two 4-bit adders.

4-7. Magnitude comparator The equality relation of each pair of bits can be expressed logically with an exclusive-NOR function as: A = A3A2A1A0 ; B = B3B2B1B0 xi=AiBi+Ai’Bi’ for i = 0, 1, 2, 3 (A = B) = x3x2x1x0

Magnitude comparator We inspect the relative magnitudes of pairs of MSB. If equal, we compare the next lower significant pair of digits until a pair of unequal digits is reached. If the corresponding digit of A is 1 and that of B is 0, we conclude that A>B. (A>B)= A3B’3+x3A2B’2+x3x2A1B’1+x3x2x1A0B’0 (A<B)= A’3B3+x3A’2B2+x3x2A’1B1+x3x2x1A’0B0

4-8. Decoders The decoder is called n-to-m-line decoder, where m≤2n . the decoder is also used in conjunction with other code converters such as a BCD-to-seven_segment decoder. 3-to-8 line decoder: For each possible input combination, there are seven outputs that are equal to 0 and only one that is equal to 1.

Implementation and truth table

Decoder with enable input Some decoders are constructed with NAND gates, it becomes more economical to generate the decoder minterms in their complemented form. As indicated by the truth table , only one output can be equal to 0 at any given time, all other outputs are equal to 1.

Demultiplexer A decoder with an enable input is referred to as a decoder/demultiplexer. The truth table of demultiplexer is the same with decoder. Demultiplexer D0 D1 D2 D3 E A B

3-to-8 decoder with enable implement the 4-to-16 decoder

Implementation of a Full Adder with a Decoder From table 4-4, we obtain the functions for the combinational circuit in sum of minterms: S(x, y, z) = ∑(1, 2, 4, 7) C(x, y, z) = ∑(3, 5, 6, 7)

4-9. Encoders An encoder is the inverse operation of a decoder. We can derive the Boolean functions by table 4-7 z = D1 + D3 + D5 + D7 y = D2 + D3 + D6 + D7 x = D4 + D5 + D6 + D7

Priority encoder If two inputs are active simultaneously, the output produces an undefined combination. We can establish an input priority to ensure that only one input is encoded. Another ambiguity in the octal-to-binary encoder is that an output with all 0’s is generated when all the inputs are 0; the output is the same as when D0 is equal to 1. The discrepancy tables on Table 4-7 and Table 4-8 can resolve aforesaid condition by providing one more output to indicate that at least one input is equal to 1.

Priority encoder V=0no valid inputs V=1valid inputs X’s in output columns represent don’t-care conditions X’s in the input columns are useful for representing a truth table in condensed form. Instead of listing all 16 minterms of four variables.

4-input priority encoder Implementation of table 4-8 x = D2 + D3 y = D3 + D1D’2 V = D0 + D1 + D2 + D3

4-10. Multiplexers S = 0, Y = I0 Truth Table S Y Y = S’I0 + SI1 S = 1, Y = I1 0 I0 1 I1

4-to-1 Line Multiplexer

Quadruple 2-to-1 Line Multiplexer Multiplexer circuits can be combined with common selection inputs to provide multiple-bit selection logic. Compare with Fig4-24. I0 Y I1

Boolean function implementation A more efficient method for implementing a Boolean function of n variables with a multiplexer that has n-1 selection inputs. F(x, y, z) = (1,2,6,7)

4-input function with a multiplexer F(A, B, C, D) = (1, 3, 4, 11, 12, 13, 14, 15)

Three-State Gates A multiplexer can be constructed with three-state gates.

Sequential logic circuits

Sequential logic circuits Outline Sequential Circuit Models Asynchronous Synchronous Latches Flip-Flops CS 3402--Digital Logic Sequential logic circuits

Sequential logic circuits The main characteristic of combinational logic circuits is that their output values depend on their present input values. Sequential logic circuits differ from combinational logic circuits because they contain memory elements so that their output values depend on both present and past input values CS 3402--Digital Logic Sequential logic circuits

Sequential logic circuits Sequential circuits can be Asynchronous or synchronous. Asynchronous sequential circuits change their states and output values whenever a change in input values occurs. Synchronous sequential circuits change their states and output values at fixed points of time, i.e. clock signals. CS 3402--Digital Logic Sequential logic circuits

Sequential Circuit Models Universal model CS 3402--Digital Logic Sequential logic circuits

Sequential logic circuits Combinational circuit model Mealy machine model Moore machine model CS 3402--Digital Logic Sequential logic circuits

Sequential Circuit Models Circuit type Excitation Output Combinational None O = g(I) Moore Machine E = f (I, St) O = g(St) Mealy Machine O = g(I, St) CS 3402--Digital Logic Sequential logic circuits

Sequential logic circuits Memory Devices Latches A latch is a memory element whose excitation signals control the state of the device. A latch has two stages set and reset. Set stage sets the output to 1. Reset stage set the output to 0. Flip-flops A flip-flop is a memory device that has clock signals control the state of the device. CS 3402--Digital Logic Sequential logic circuits

Sequential logic circuits Latch Flip-flop CS 3402--Digital Logic Sequential logic circuits

Latch and Flip-Flop Devices # of Elements Description 74LS73A 2 Negative-edge triggered JK flip-flop with clear 7474 Positive-edge triggered D flip-flop with preset and clear 74LS75 4 D Latch with enable 7476 Pulse-edge triggered JK flip-flop with preset and clear 74111 Master-slave JK flip-flop with preset, clear, and data lock out 74116 4-bit hazard-free D latch with clear and dual enable 74175 Positive-edge triggered D flip-flop with clear 74273 8 74276 Negative-edge triggered JK flip-flop with preset and clear 74279 SR latch with active-low inputs CS 3402--Digital Logic Sequential logic circuits

Sequential logic circuits Inverter Chains Ring oscillator CS 3402--Digital Logic Sequential logic circuits

Sequential logic circuits Latches RS Latch The RS latch is the basic memory element consists of two cross-coupled NOR gates. It has two input signals, S set signal and R reset signal. It also has two outputs Q and Q'; and two states, a set state when Q = 1 and a reset state when Q = 0 (Q' = 1) CS 3402--Digital Logic Sequential logic circuits

Sequential logic circuits 1 S R Q hold 1 0 reset 1 set unstable CS 3402--Digital Logic Sequential logic circuits

Sequential logic circuits Theoretical state diagram of cross-coupled NOR gates CS 3402--Digital Logic Sequential logic circuits

Sequential logic circuits Observed state diagram of cross-coupled NOR gates CS 3402--Digital Logic Sequential logic circuits

RS Latch excitation table Q(t) Q(t+1) Hold 1 Reset Q(t+1) = S(t) + R'(t)Q(t) Set Q+ = S+ R'Q X Forbidden CS 3402--Digital Logic Sequential logic circuits

Sequential logic circuits 1 S R Q unstable 1 0 reset 1 set hold CS 3402--Digital Logic Sequential logic circuits

State, Clock, Setup Time, and Hold Time The Clocking event can be either from low to high or from high to low. The input signal around clocking event must remain unchanged in order to have a correct effect on the outcome of the new state. Tsu: the minimum time interval preceding the clocking event during the input signal must remain unchanged Th: the minimum time interval after edge of the clocking event during the input signal CS 3402--Digital Logic Sequential logic circuits

Timing Diagram of RS-Latch CS 3402--Digital Logic Sequential logic circuits

Sequential logic circuits JK Latch S R Q(t) Q(t+1) Hold 1 Reset Set Q+ = K'Q+ JQ' toggle CS 3402--Digital Logic Sequential logic circuits

Level-Sensitive Latches A level-sensitive latch is a latch with an additional enable input. RS latch CS 3402--Digital Logic Sequential logic circuits

Sequential logic circuits RS Latch with Enable C S R Q(t) Q(t+1) X Hold 1 Reset Set toggle CS 3402--Digital Logic Sequential logic circuits

Sequential logic circuits D Latch C D Q(t) Q(t+1) X Hold 1 Reset Set Q+ = D CS 3402--Digital Logic Sequential logic circuits

Sequential logic circuits Flip-Flops A flip-flop is a level-sensitive latch with a clock input. RS flip-flop Q+ = S +R'Q CS 3402--Digital Logic Sequential logic circuits

Sequential logic circuits T (Toggle) flip-flop D Q(t) Q(t+1) Hold 1 Toggle Q+ = TQ' + T'Q CS 3402--Digital Logic Sequential logic circuits

Master Slave Flip-Flops A master slave flip-flop consists of two latches and an inverter. Master-slave RS flip-flop CS 3402--Digital Logic Sequential logic circuits

Master-Slave JK Flip-Flops CS 3402--Digital Logic Sequential logic circuits

Sequential logic circuits CS 3402--Digital Logic Sequential logic circuits

Positive Edge-Triggered Flip-Flops Positive edge-triggered RS flip-flop timing diagram CS 3402--Digital Logic Sequential logic circuits

Sequential logic circuits Positive edge-triggered JK flip-flop timing diagram CS 3402--Digital Logic Sequential logic circuits

Sequential logic circuits Positive edge-triggered D flip-flop timing diagram CS 3402--Digital Logic Sequential logic circuits

Positive Edge-Triggered Timing A circuit that generates a positive edge-triggered timing signal can be constructed as follows: CS 3402--Digital Logic Sequential logic circuits

When inputs are sampled Type When inputs are sampled When outputs are valid Unclocked latch Always Propagation delay from input change Level-sensitive latch Clock high Positive-edge latch Clock low-to-high transition Propagation delay from rising edge of clock Negative-edge latch Clock high-to-low transition Propagation delay from falling edge of clock Master/slave flip-flop CS 3402--Digital Logic Sequential logic circuits

Sequential logic circuits Exercises page 425, 6.1-6.6, 6.9, 6.10, 6.12, 6.13, 6.14, 6.17, 6.24, 6.25 CS 3402--Digital Logic Sequential logic circuits