Sequential Statements (Lecture 2)

Slides:



Advertisements
Similar presentations
Logic Circuits Design presented by Amr Al-Awamry
Advertisements

Give qualifications of instructors: DAP
Lecture # 21 Chapter 6 Uptill 6.4. Type System A type system is a collection of rules for assigning type expressions to the various parts of the program.
Lecture 6 Chap 8: Sequential VHDL Instructors: Fu-Chiung Cheng ( 鄭福炯 ) Associate Professor Computer Science & Engineering Tatung University.
Dr. Yang, Qingxiong (with slides borrowed from Dr. Yuen, Joe) LT4: Control Flow - Loop CS2311 Computer Programming.
Chapter 4 Control Structures I. Objectives ► Examine relational and logical operators ► Explore how to form and evaluate logical (Boolean) expressions.
CS 151 Digital Systems Design Lecture 37 Register Transfer Level
All the Operators. Precedence An operator with higher precedence is done earlier (prededes) one with lower precedence –A higher precedence is indicated.
All the Operators. Precedence An operator with higher precedence is done earlier (prededes) one with lower precedence –A higher precedence is indicated.
Dr. Turki F. Al-Somani VHDL synthesis and simulation – Part 3 Microcomputer Systems Design (Embedded Systems)
Combinational Logic Chapter 4.
CSC 200 Lecture 4 Matt Kayala 1/30/06. Learning Objectives Boolean Expressions –Building, Evaluating & Precedence Rules Branching Mechanisms –if-else.
Formal verification Marco A. Peña Universitat Politècnica de Catalunya.
Fall 08, Oct 29ELEC Lecture 7 (updated) 1 Lecture 7: VHDL - Introduction ELEC 2200: Digital Logic Circuits Nitin Yogi
Introduction to VHDL (part 2)
EGR 2261 Unit 4 Control Structures I: Selection  Read Malik, Chapter 4.  Homework #4 and Lab #4 due next week.  Quiz next week.
RTL Hardware Design by P. Chu Chapter Derivation of efficient HDL description 2. Operator sharing 3. Functionality sharing 4. Layout-related circuits.
ENG6090 RCS1 ENG6090 Reconfigurable Computing Systems Hardware Description Languages Part 4: Modeling Dataflow.
Combinational Logic Chapter 4. Digital Circuits Combinational Circuits Logic circuits for digital system Combinational circuits the outputs are.
A.7 Concurrent Assignment Statements Used to assign a value to a signal in an architecture body. Four types of concurrent assignment statements –Simple.
Chapter 4: Control Structures I (Selection). Objectives In this chapter, you will: – Learn about control structures – Examine relational operators – Discover.
Chapter 4: Control Structures I (Selection). Objectives In this chapter, you will: – Learn about control structures – Examine relational and logical operators.
Sequential Statements
VHDL Introduction. V- VHSIC Very High Speed Integrated Circuit H- Hardware D- Description L- Language.
ECE Advanced Digital Systems Design Lecture 4 – Combinational Circuits in VHDL Capt Michael Tanner Room 2F46A HQ U.S. Air Force Academy.
Controlling Execution Programming Right from the Start with Visual Basic.NET 1/e 8.
Control Structures sequence of execution of high-level statements.
15-Nov-15 All the Operators. operators.ppt 2 Precedence An operator with higher precedence is done earlier (precedes) one with lower precedence A higher.
COE 202 Introduction to Verilog Computer Engineering Department College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals.
1 ECE 545 – Introduction to VHDL Dataflow Modeling of Combinational Logic Simple Testbenches ECE 656. Lecture 2.
Software Defects.
1 Predicate Abstraction and Refinement for Verifying Hardware Designs Himanshu Jain Joint work with Daniel Kroening, Natasha Sharygina, Edmund M. Clarke.
Introduction to VHDL Simulation … Synthesis …. The digital design process… Initial specification Block diagram Final product Circuit equations Logic design.
Chapter 4 Control Structures I. Chapter Objectives Learn about control structures Examine relational and logical operators Explore how to form and evaluate.
Chapter 4: Control Structures I (Selection). Objectives In this chapter, you will: – Learn about control structures – Examine relational and logical operators.
George Mason University Data Flow Modeling in VHDL ECE 545 Lecture 7.
COIT29222 Structured Programming 1 COIT29222-Structured Programming Lecture Week 02  Reading: Textbook(4 th Ed.), Chapter 2 Textbook (6 th Ed.), Chapters.
CS/EE 3700 : Fundamentals of Digital System Design
EE121 John Wakerly Lecture #17
ECOM 4311—Digital System Design with VHDL
Data Flow Modeling in VHDL
RTL Hardware Design Chapter Combinational versus sequential circuit 2. Simple signal assignment statement 3. Conditional signal assignment statement.
Java Basics. Tokens: 1.Keywords int test12 = 10, i; int TEst12 = 20; Int keyword is used to declare integer variables All Key words are lower case java.
George Mason University Data Flow Modeling of Combinational Logic ECE 545 Lecture 5.
Logic Design (CE1111 ) Lecture 4 (Chapter 4) Combinational Logic Prepared by Dr. Lamiaa Elshenawy 1.
COSC2410: LAB 2 BINARY ARITHMETIC SIGNED NUMBERS FLOATING POINT REPRESENTATION BOOLEAN ALGEBRA 1.
Chapter 4: Control Structures I (Selection). Objectives In this chapter, you will: – Learn about control structures – Examine relational operators – Discover.
Hardware Description Languages: Verilog
Combinational logic circuit
Def: A control structure is a control statement and
Introduction Introduction to VHDL Entities Signals Data & Scalar Types
Hardware Description Languages: Verilog
Sequential Design.
Bools & Ifs.
Behavioral Modeling in Verilog
Chapter 4: Control Structures I (Selection)
Introduction to Programming
ECE 551: Digital System Design & Synthesis
EGR 2131 Unit 8 VHDL for Combinational Circuits
Data Flow Modeling of Combinational Logic
VHDL (VHSIC Hardware Description Language)
Ch 4. Combinational logic
CS/COE0447 Computer Organization & Assembly Language
CS/COE0447 Computer Organization & Assembly Language
ECE 331 – Digital System Design
Data Flow Description of Combinational-Circuit Building Blocks
VHDL Programming (08 Marks)
Data Flow Description of Combinational-Circuit Building Blocks
Assertions References: internet notes; Bertrand Meyer, Object-Oriented Software Construction; 4/25/2019.
VHDL - Introduction.
Presentation transcript:

Sequential Statements (Lecture 2) Osman Hasan COEN 313

Outline If statement Case Statement For loop Statement

If Statement Sequential Conditional Statement in VHDL Syntax if boolean_expr_1 then sequential_statements; elsif boolean_expr_2 then elsif boolean_expr_3 then . . . else end if; Safety critical system failure could cause human life. Commercial critical systems: great financial loss if the product is recalled or is found to contain bugs Examples of undetected errors – Ariane 5 rocket explosion, 1996 (exception occurred when converting 64-bit floating number to a 16-bit integer) – Pentium bug (multiplier table not fully verified) – many more …. Somehow make debugging happen earlier where it is cheaper 3 3

If Statement – Conceptual implementation Safety critical system failure could cause human life. Commercial critical systems: great financial loss if the product is recalled or is found to contain bugs Examples of undetected errors – Ariane 5 rocket explosion, 1996 (exception occurred when converting 64-bit floating number to a 16-bit integer) – Pentium bug (multiplier table not fully verified) – many more …. Somehow make debugging happen earlier where it is cheaper 4 4

If Statement – Comparison to conditional signal assignment If statement is more flexible Multiple Statements may share the same Boolean Condition Nesting Safety critical system failure could cause human life. Commercial critical systems: great financial loss if the product is recalled or is found to contain bugs Examples of undetected errors – Ariane 5 rocket explosion, 1996 (exception occurred when converting 64-bit floating number to a 16-bit integer) – Pentium bug (multiplier table not fully verified) – many more …. Somehow make debugging happen earlier where it is cheaper 5 5

If Statement – “sharing” Boolean condition Example Safety critical system failure could cause human life. Commercial critical systems: great financial loss if the product is recalled or is found to contain bugs Examples of undetected errors – Ariane 5 rocket explosion, 1996 (exception occurred when converting 64-bit floating number to a 16-bit integer) – Pentium bug (multiplier table not fully verified) – many more …. Somehow make debugging happen earlier where it is cheaper 6 6

Quiz 1: Maximum of 3 numbers c VHDL (Using If statemets) max Safety critical system failure could cause human life. Commercial critical systems: great financial loss if the product is recalled or is found to contain bugs Examples of undetected errors – Ariane 5 rocket explosion, 1996 (exception occurred when converting 64-bit floating number to a 16-bit integer) – Pentium bug (multiplier table not fully verified) – many more …. Somehow make debugging happen earlier where it is cheaper 7 7

Common Mistakes! Incomplete Branch Equality Checker ‘0’

Common Mistakes! Incomplete Signal Assignment Equality/Inequality Checker

Outline If statement Case Statement For loop Statement 10 10

Case Statement Sequential Conditional Statement in VHDL Syntax case case_expression is when choice_1 => sequential statements; when choice_2 => . . . when choice_n => end case; Safety critical system failure could cause human life. Commercial critical systems: great financial loss if the product is recalled or is found to contain bugs Examples of undetected errors – Ariane 5 rocket explosion, 1996 (exception occurred when converting 64-bit floating number to a 16-bit integer) – Pentium bug (multiplier table not fully verified) – many more …. Somehow make debugging happen earlier where it is cheaper 11 11

Case Statement – Conceptual implementation Safety critical system failure could cause human life. Commercial critical systems: great financial loss if the product is recalled or is found to contain bugs Examples of undetected errors – Ariane 5 rocket explosion, 1996 (exception occurred when converting 64-bit floating number to a 16-bit integer) – Pentium bug (multiplier table not fully verified) – many more …. Somehow make debugging happen earlier where it is cheaper 12 12

Example: 4x1 Mux Safety critical system failure could cause human life. Commercial critical systems: great financial loss if the product is recalled or is found to contain bugs Examples of undetected errors – Ariane 5 rocket explosion, 1996 (exception occurred when converting 64-bit floating number to a 16-bit integer) – Pentium bug (multiplier table not fully verified) – many more …. Somehow make debugging happen earlier where it is cheaper 13 13

Example: 2x4 Binary Decoder Safety critical system failure could cause human life. Commercial critical systems: great financial loss if the product is recalled or is found to contain bugs Examples of undetected errors – Ariane 5 rocket explosion, 1996 (exception occurred when converting 64-bit floating number to a 16-bit integer) – Pentium bug (multiplier table not fully verified) – many more …. Somehow make debugging happen earlier where it is cheaper 14 14

Example: 4-to-4 Priority Encoder Safety critical system failure could cause human life. Commercial critical systems: great financial loss if the product is recalled or is found to contain bugs Examples of undetected errors – Ariane 5 rocket explosion, 1996 (exception occurred when converting 64-bit floating number to a 16-bit integer) – Pentium bug (multiplier table not fully verified) – many more …. Somehow make debugging happen earlier where it is cheaper 15 15

Common Mistakes! Incomplete Branch not possible Incomplete Signal Assignment

Common Mistakes! Incomplete Signal Assignment Solution 1

Common Mistakes! Incomplete Signal Assignment Solution 2

Outline If statement Case Statement For loop Statement 19 19

For-Loop Statement Looping in VHDL Syntax for index in loop_range loop sequential statements; end loop; Safety critical system failure could cause human life. Commercial critical systems: great financial loss if the product is recalled or is found to contain bugs Examples of undetected errors – Ariane 5 rocket explosion, 1996 (exception occurred when converting 64-bit floating number to a 16-bit integer) – Pentium bug (multiplier table not fully verified) – many more …. Somehow make debugging happen earlier where it is cheaper 20 20

For-Loop Statement – Conceptual implementation For loop should be treated as “shorthand” for repetitive statements E.g., bit-wise xor Safety critical system failure could cause human life. Commercial critical systems: great financial loss if the product is recalled or is found to contain bugs Examples of undetected errors – Ariane 5 rocket explosion, 1996 (exception occurred when converting 64-bit floating number to a 16-bit integer) – Pentium bug (multiplier table not fully verified) – many more …. Somehow make debugging happen earlier where it is cheaper 21 21

Summary Concurrent statements Sequential statements Have clear, direct mapping to physical structures Difficult to represent complex behaviors Sequential statements Flexible and versatile Resulting hardware may not be very straight forward at times Can be easily abused 22