Optimum Dispatch of Capacitors in Power Systems The Hong Kong Polytechnic University Department of Electrical Engineering Optimum Dispatch of Capacitors in Power Systems Final Year Project Higher Diploma In Electrical Engineering FAN Ming Yiu IP Ching To 15080338D 15081731D

Problem formula

Problem formula Objective: Minimize 𝑃 𝑡𝑜𝑡𝑎𝑙−𝑙𝑜𝑠𝑠 = ℎ𝑟=0 23 𝑃 𝐿𝑜𝑠𝑠 (ℎ𝑟,𝑆(ℎ𝑟)) Constrains:   𝑉 𝑗 = 𝑉 𝑛𝑎𝑚 ±6% 𝑓𝑜𝑟 𝑗=0,1,2…, 𝑛 𝑛𝑜𝑑𝑒 ℎ𝑟=0 23 𝑂𝑝(𝑖)≤𝐾 𝑓𝑜𝑟 𝑖=0,1,2,…, 𝑛 𝑐𝑎𝑝𝑎𝑐𝑖𝑡𝑜𝑟

Distribution system model

Power flow solution: Direct Gauss Method Pros: -idea is simple Cons: -The number of iterate is growing as the system size is growing.

Power flow solution: Newton-Raphson Method Pros: -less number of iteration is need for a large size of distribution system Cons: -Computing cost is high for Taylor’s series expansion matrix.

Power flow solution: Fast Decoupled Power-Flow Method Pros: -the computing time is very fast as the complexity of calculation is low Cons: -the method is based on some assumption, which means the result should be slightly different to the real situation.

Power flow solution: Conclusion Distribution model is small size and simple Direct Gauss Method is used Simple Faster construction

Optimize method: Branch and Bound Algorithm: Build up a BnB tree Branch the root with adding one specific situation. Heapifty BnB tree with Heapsort Repeat above two step until complete solution .

Optimize method: Branch and Bound Algorithm: Pros: -Compute time is less in general case. Cons: -The compute time on same complexity problem can be huge different because of the unstable compute time of Branch and Bound. -The additional operation of heapsort are required and caused increase the compute time

Optimize method: Dynamic Programming Algorithm breaking the problem in to sub-problems Solves and save the sub-problems one by one. Recursion to get the solution

Optimize method: Dynamic Programming Algorithm Pros: -Very stable compute time Cons: -Many unnecessary nodes generated and occupy the major compute time on handling the node operation. -Large memory space is need for saving sub-problem

The optimize method: Conclusion of choosing Branch and bound ->trying data systematically Dynamic Programming ->calculating all possible solutions. stable compute time> small advantage of faster compute time.

Methodology: a program of generate optimal capacitor dispatch schedule is developed. Direct Gauss Method to calculate the power flow solution, Dynamic Programming to optimize solution of capacitor state. C++ as programing langue object-orientated programing Support pointer

Methodology: modify of problem Total power loss of a day->sum of power loss at each hour(sub-problem) For dynamic programming the on/off capacitor state-> the number of operation For minimize memory space

Methodology: Structure optimal solution finder power flow solution solver

Methodology: Part 1: Read raw data import the essential raw data from 2 external file system characteristic power Load reduce the time of data inputting In fixed format and fixed sequence

Methodology: Part3: Generate node Will generate all nodes at each state   𝑛 𝑛𝑜𝑑𝑒 = (𝑖+1) 𝑛 𝑐𝑎𝑝 𝑓𝑜𝑟 𝑖<𝐾,𝑖=0,1…,23 𝑛 𝑛𝑜𝑑𝑒 = (𝐾+1) 𝑛 𝑐𝑎𝑝 𝑓𝑜𝑟 𝑖≥𝐾 allocating memory Part4: Initiate state

Methodology: Part5: Allocate capacitor state generate all combination of the capacitor operation allocate the capacitor state to node one by one

Power Loss Calculation Power loss and voltage calculated Direct Gauss iterative Method used Ignore power loss of line at the first time iteration End iteration if solution converges

Methodology: Part7: Node Linking Find out the optimal pervious node by compare all pervious capacitor state

Methodology: Part7: Node Linking Update the pervious pointer Update the accumulate power loss sum of the self-real power line loss the pervious accumulated real power line loss.

Methodology: Part8: Generate Schedule Find the optimal node at stage 3 Forward recursion for the node until complete schedule generated

Result and finding

Variable #N: Number of nodes (including the base voltage point) #Bn: Line impedance component of section that from node n to node (n+1) (left is resistance, right is reactance) #num_C: Number of shunt capacitor banks #C_posn: Position of the shunt capacitor banks (n starts from 0) #C_Varn: The var rating of the shunt capacitor banks (n starts from 0) #base_V: The base voltage (voltage entering the distribution feeder) #Max_op: Maximum operation of each shunt capacitor banks (value K)

Result and finding Computing time: K=1 K=2 K=3

Result and finding t K -Large number of comparison of cases occur causing the exponential increase of computing time

Result and finding Number of section increase ,the computing time will also increase Number of section =8

Result and finding Changing the location of capacitor banks does not affect the computing time. But the power loss may be different due to different power factor correction

Result and finding Sometimes the power loss may be larger even with capacitor banks of higher KVAr rating 65616.5W loss 250KVAr 67701.6W loss 500KVAr 99536.9W loss 1000KVAr Other variables are unchanged

Result and finding LP j = 𝑅 𝑗 [ 𝑃 2 𝑚2 + 𝑄 2 (𝑚2)] 𝑉(𝑚2) 2 Q (m2) ^2=(Qload - Qcapacitor)^2 If Q (m2) is a small +ve or –ve number, power loss will be small If Qcapacitor so large, Q (m2) become a large negative number, the power loss will be so high

Result and finding The value of K increases, the power loss will decrease 261169W K=1 254119W K=2 253170W K=3

Result and finding The shunt capacitor banks can provide a more flexible arrangement of the power factor correction.

End