FLIPPED CLASSROOM ACTIVITY CONSTRUCTOR – USING EXISTING CONTENT

V.PERUMAL CACHE MEMORY COMPUTER ARCHITECTURE CSE II Year Computer Science Engineering Students CSE/Saveetha Engineering College

Out-of-class Activity Design -1 Learning Objective(s) of Out-of-Class Activity At the end of watching the videos student should be able to What do you meant by cache? Purpose of Cache How the access time of CPU increases because of Cache ? Mapping and its types Performance of Cache Direct Mapping Technique Able to identify the Cache position of given block number in Main memory Key Concept(s) to be covered Cache Memory Performance of Cache Mapping technique

Out-of-class Activity Design - 2 Main Video Source URL https://seciitbx.wordpress.com/ License of Video My own video/ PPT Show Mapping Concept to Video Source CONCEPT VIDEO SEGMENT DURATION (in min) Cache Basics V1-0.00 to 5:22 5:22 Min Performance of Cache Direct Mapping Technique V2- 5:23 to 10:28 5:06 Min TOTAL DURATION 10:28 Min

Out-of-class Activity Design - 3 Aligning Assessment with Learning Objective Learning Objective Assessment Strategy Expected duration (in min) Additional Instructions (if any) Performance of Cache 1. Find the AMAT of a processor with clock cycle time: 1ns, Miss penalty :20 clock cycles, miss rate:0.05 misses / instruction hit rate:1 clock cycle 2 minutes Block Position in Cache Main memory Capacity 64KB with 4096 Blocks and 16 words/block. Cache size 2KB with 128 blocks and 16 words/block. Find the Position of Block 1347 in cache. 4 minutes Direct Mapping Main memory Capacity 32KB with 4096 Blocks and 8 words/ block. Cache size 2KB with 256 blocks and 8 words/ block. Then Find the number of bits required for the following fields in Main memory Address. Watch V1 and then answer Q1 Watch V2 and then answer Q2 Watch V2 and then answer Q3 Expected activity duration 10:28 Min

In-class Activity Design -1 Learning Objective(s) of In - Class Activity Able to design the Cache memory with Direct Mapping techniques in real time scenario. Key Concept(s) to be covered Defining the Main memory Address bits with different sizes of different field by designing Cache memory .

In-class Activity Design -2 Active Learning activity(ies) that you plan to do Active Learning Strategy Explain the strategy by giving details of What Teacher will do? What Student will do? Justify why the above is an active learning strategy Enter Justification Here

In-class Activity Design -2 Active Learning activity(ies) that you plan to do Problem solving using. Think-Pair-Share Concept clarification using. Peer Instruction

In-class Activity Design -2 Peer Instruction Strategy – What Teacher Does Asked a Student to give a summary of Direct Mapping technique and then posted a question on that topic. Q 1: How many total bits are required for a direct-mapped cache with 128 KB of data and 8-word block size, assuming a 32-bit address? . 

In-class Activity Design -2 Peer Instruction Strategy – What Student Does First asked the students to give their answer individually. Then asked them to discuss among themselves about the correct answer. For any clarification the have to listen to instructors explanation.