SVT-Attivita’ e preventivi INFN 2012 June, 8 2011 Update on TDR activities  end of 2011 Construction phases & prototypes needed in 2012 to switch to production in 2013 Giuliana Rizzo Universita’ & INFN Pisa G. Rizzo SVT –Preventivi 2012, June 8 - 2011

Slides presented at the Tech Board in Elba – June 2nd 2011 Transition from TDR to Construction Schedule for Baseline (SVT+striplets) Schedule for Pixel upgrade Construction responsibility: first attempt G. Rizzo SVT –Preventivi 2012, June 8 - 2011

Introduction by Forti/Ratcliff at the Techboard TDR timeline July 2011: initial outline. Main section editors Sett 2011: Detailed outline and editorial responsibility. Tentative institutional matrix of responsibility and money allocation. Dec 2011 first (in)complete draft. Updated budget & schedule for construction. Feb 2012 complete draft to final editing April 2012 publish G. Rizzo SVT –Preventivi 2012, June 8 - 2011

Work to be done for TDR (I) Institute already involved Potential new collaborators for construction Sensors: striplets & optimization of detectors models for L1-5: Trieste Silicon Sensors Suppliers investigated Optimization of geometrical size L1-L5 will start after better definition of geometrical/mechanical module design. (Oct 2011) Iterest from UK – QM. Readout chip (striplets/strip) - critical Definition of the requirements for readout chips for strips: Need to develop 2 new chips (L0-1-3 + L4-5) since existent chips do not match all the requirements: First estimate of noise vs shaping time in each layer done: some optimization still needed. PV group + interest from another group in Milano. Started to evaluate if readout architecture for pixels can be used for strips as well: no evident showstopper up to now (Pisa/Bologna) For TDR full VHDL simulation of the chips can be done (PV/PI/BO) starting this autumn  spring 2012. For real chip development/construction need to get new groups on board! G. Rizzo SVT –Preventivi 2012, June 8 - 2011

Voltage regulator, DC-DC?, serializer, LVDS PV/BG/MI Pisa Bologna New manpower joining Voltage regulator, DC-DC?, serializer, LVDS G. Rizzo SVT –Preventivi 2012, June 8 - 2011

Work to be done for TDR (II) On detector electronics: Fanout/HDI/transition cards+links (Milano) Activity proceed and TDR design can be completed by spring 2012 with the right manpower available (1 FTE avail. 1 eng left need a replacement) (M. Citterio) Iterest from University of Insubria (MI) to join on these items (from 2012). Explore interest from other non IT institutes. DAQ: development of the SVT FEB (Bologna) Some of the work can be done only after a clear definition of some common SuperB components (FCTS, ECS, links). TDR design can be completed in spring 2012 (M. Villa) More manpower will help! (FE chips development also in Bologna) Mechanics: F. Bosi Progress in the design of striplets modules for Layer0 & definition of the full envelop for the entire SVT. New manpower from UK (QM) on the design of the SVT mechanics (support cones and space frames). Fruitful meeting in May in Pisa to get started More manpower is needed in Pisa (+1 eng with position available) G. Rizzo SVT –Preventivi 2012, June 8 - 2011

Pixel for Layer0 Clearer definition of requirements for Layer0 pixels: Background (x5 safety included) Rate ~100-300 MHz/cm2 depends on radius and sensor thickness Timestamp of 1 us  5-10 Gbit/s link TID ~ 15Mrad/yr Eq. neutron fluence: 2.5 1013 n/cm2/yr Standard CMOS MAPS marginal Physics: Resolution of 10-15 um in both coordinates Total material budget <= 1% X0 Radius ~1.3-1.5 cm Several options still open & under development  decision on technology in 2013 Hybrid pixels: more mature and rad hard but with higher material budget R&D on FE chip 50x50 um pitch with fast readout ongoing (INFN – SuperB SVT group) Pixel module design with ~ 1% X0 with present technology Evaluate reduction of material in silicon & pixel bus: ALICE ITS upgrade (Bari interest) CMOS MAPS: newer technology potentially very thin, readout speed and rad hardness challenging for application in Layer0. R&D on DNW MAPS with sparsified fast readout well advanced (INFN – SuperB SVT group) New submission in July with INMAPS CMOS process with high resistivity substrate & quadruple well to improve radiation hardness & charge collection efficiency. Other groups interested in MAPS option for Layer0: RAL + Strasbourg G. Rizzo SVT –Preventivi 2012, June 8 - 2011

BABAR experience SuperB SVT + striplets BaBar FE chips status   BABAR experience BaBar FE chips status SuperB SVT + striplets FE chips status (assuming 2 yrs for chip starting in 2012) yr item 94 chip design rad soft 2011 fanouts, HDI prototypes start chips FE simulation of architecture 95 design Si sensors, fanout other components 2012 design sensor fanouts HDI transition cards, produce modules prototypes first cell prototypes on chosen technology for strip FE + first chip protoype end of 2012 96 first detectors available spring chip design rad hard 2013 submit for production sensor fanout HDI + start test sensor fanout first prototypes chips 97 start DFA production and HDI construction 2014 production run 98 HDI loading with chips + DFA+HDI+Arch production chips available 2015 99 jan-march module installation, june start data taking 2016 final assembly (3 m) SVT, installation, start data taking summer G. Rizzo SVT –Preventivi 2012, June 8 - 2011

MAPS Hybrid pixels yr item 2011 MAPS 180 nm 1st prototype   MAPS Hybrid pixels yr item 2011 MAPS 180 nm 1st prototype Chartered/Tezzaron FE 3D chip 2012 MAPS 180 nm sensing optimization continue R&D on bump bonding with thin sensor FE chartered tezzaron (new submmission of FE chips with possible different technology IBM 130 nm?) 2013 MAPS approved for Layer0 (3 yrs full development) first MPW large scale If MAPS are not ok decide for hybrid pixel and choose technology cost of production run + 3 yrs (2?) to final production. Ist prototype large scale 2014 MAPS first production run FE chip HP first production run 2015 MAPS final production run FE chip HP final production run 2016 MAPS module assembly HP module assembly (1-2 yrs???) 2017 data taking with MAPS data taking with HP G. Rizzo SVT –Preventivi 2012, June 8 - 2011

SVT WBS from White Paper G. Rizzo SVT –Preventivi 2012, June 8 - 2011

Construction Responsibility & Schedule From BaBar experience ~ 5 yrs from design to data taking Construction phases: Design & prototype: 2012 baseline, 2012 R&D on upgrade to pixel L0: technology choice in 2013 Procure and Fabricate (+test) (2013-2014) 2013-2014-2015 for pixel upgrade Module Assembly & Detector Assembly (2015) 2016 for pixel upgrade Commissioning 2016 2017 possible installation of pixel Main assumption for this schedule 2 main labs (baseline): BABAR Silicon sensors: Pisa+Trieste On detector electronics: FE Chips LBL+PV HDI: MI SVT DAQ + peripheral electr.: UCSC Module assembly: Pisa+UCSB SVT Mechanics: LBL+ IT (PI/ FE/TO) SuperB Silicon sensors: Trieste + QM? On detector electronics: Pixel Chips PV/PI/BO + others FE chips strips ?? Peripheral electr.: MI SVT DAQ: BO Module assembly: Pisa + UK? or others? SVT Mechanics: Pisa + QM? G. Rizzo SVT –Preventivi 2012, June 8 - 2011

Construction Responsibility – First attempt * ** * G. Rizzo SVT –Preventivi 2012, June 8 - 2011

List of topics for new collaborators FE readout chips for strip detectors Modules assembly and testing (as in BaBar 2 groups are needed) SVT Mechanics: more manpower needed Engineering design of Layer1-5 modules … Peripheral electronics: more manpower useful SVT SW G. Rizzo SVT –Preventivi 2012, June 8 - 2011

SVT Institutions Groups already working for the SVT: Bologna: SVT DAQ , MAPS & FE chips (digital architecture). Milano: fanout/pixel bus & peripheral electronics, SVT performance studies. Pavia/BG: MAPS & FE chips (analog cells) Pisa: SVT coordination, MAPS & FE chips (in-pixel logic and digital architecture), module assembly & testing, SVT mechanics and cooling, testbeams. RomaIII: MAPS Trieste: Silicon sensors, striplets module, fanout Torino: testbeams mechanics. « New » groups getting involved: UK: QM (SVT mechanics, sensors? ), RAL (MAPS) Strasbourg (MAPS) Bari (Hybrid Pixel?) University of Insubria (fanout) Milano FE chips (analog cell) G. Rizzo SVT –Preventivi 2012, June 8 - 2011

Attivita’ da completare nel 2011 Finanziamenti di Maggio in CSNI per produzione prototipi: Modulo a pixel multichip (MI-PI) + test (???) Modulo a striplets meccanico (double layer mechanical fanout) con appoggio su flange fredde e pipe in lega leggera (PI 10+8 kE) Archi layer esterni (PI 12kE) Fanout e HDI Layer0 (MI 8+13kE) Tails & transition cards components (MI 7+11kE+18kE SW) Fanout & tails layer esterni (TS 7+5kE) SVT DAQ board development (BO?) Vorrei capire da voi il piano di attivita’ per completare i prototipi nel 2011. G. Rizzo SVT –Preventivi 2012, June 8 - 2011

Attivita’ da completare nel 2011 Finanziamenti di Maggio in CSNI per produzione prototipi: Modulo a pixel multichip (MI-PI) + test (???) Modulo a striplets meccanico (double layer mechanical fanout) con appoggio su flange fredde e pipe in lega leggera (PI 10+8 kE) Archi layer esterni (PI 12kE) Fanout e HDI Layer0 (MI 8+13kE) Tails & transition cards components (MI 7+11kE+18kE SW) Fanout & tails layer esterni (TS 7+5kE) SVT DAQ board development (BO?) Vorrei capire da voi il piano di attivita’ per completare i prototipi nel 2011. G. Rizzo SVT –Preventivi 2012, June 8 - 2011

Altre attivita’ 2011 per finalizzazione TDR  dec 2011 – feb 2012 Simulazione architettura chip FE per strips Ottimizzazione S/N celle analogiche Meccanica SVT per TDR: design moduli layer1-5 ?? Finalizzazione Layer0 striplets e accoppiamento beampipe SVT installation procedure & quick demounting Ottimizzazione geometria sensori a strip Design per TDR dei fanout (non finale ma credibile) Testbeam e analisi dati Preparazione sottomissione Chartered/Tezzaron Stesura TDR! G. Rizzo SVT –Preventivi 2012, June 8 - 2011

SVT Activities in 2012 Construction phases (from BaBar experience) Design & prototype: 2012 baseline, 2012 R&D on pixels for L0 upgrade: technology choice in 2013 Procure and Fabricate (+test) (2013-14) 2013-2014-2015 for pixel upgrade Module Assembly & Det. Assembly (2015) 2016 for pixel upgrade Commissioning 2016 2017 possible installation of pixel We enter in construction phase “Design & Prototype” For the baseline several prototypes need to be build before starting the real production in 2013 For pixels 2012 is still for R&D need some funding a first look at the schedule: G. Rizzo SVT –Preventivi 2012, June 8 - 2011

SVT prototypes in 2012 – Baseline SVT Baseline: prototypes to be built in 2012: Sensors? Double layer fanout for striplets (capacitance measurements??) FE chips for strip detector: first prototype(s) with analog cell + readout architecture (16 ch)? HDI, transition cards? DAQ? Mechanics? Finalizzazione L0 striplets module con dettagli finali per produzione Test continuita’ supporti per pixel con cooling Do we need a testbeam in 2012: The only possibility to have INMAPS structures on beams before the decision about pixel technology in 2013. First attempt, need your inputs! G. Rizzo SVT –Preventivi 2012, June 8 - 2011

SVT prototypes in 2012 – Pixels Pixel options (prototypes needed for final decision on technology in 2013: MAPS vs HP): Irradiation of INMAPS structures Second run with INMAPS process (25 mm2 ~ 70 kE) In 2012 will have a second prototype of FE chip for HP in Chartered/Tezzaron process: do we need to foresee also a submission in a standard 2D CMOS 130 nm process ? If in 2013 we decide to go for HP and need to change process the schedule seems tight. Which blocks are missing for a real chip? Voltage regulator etc need to understand if we can benefit from CERN experience Thinner Pixel bus ? Bump bonding with thinner sensor/FE chips? Investigate options for sensors: sensor thinning after bumping  p on n sensors with epitaxial layer, need different polarity for signal on FE chips, can we manage it in new Superpix1? Bari also proposed to couple our FE chip with edgless detector under design now (p on n ! Again). First attempt, need your inputs! G. Rizzo SVT –Preventivi 2012, June 8 - 2011

Schedule of next SVT meetings “Preventivi 2012” First SVT PI’s meeting ~ June 8 Try to fill in the lists in slide 5-6 First SuperB PI’s meeting June 16 in Rome Need to have a first estimate of funding requests by Tuesday 13 from all the SVT institutions. Next SVT PI’s meeting ~ June 24-29-30-1 Details of funding requests needed by that date Probably need a new iteration in the first days of July. I would like to finalize the SVT requests by July 8. G. Rizzo SVT –Preventivi 2012, June 8 - 2011

SVT Organization -TDR phase (in place since April 2009) System convener: G. Rizzo Sensors: L. Bosisio Front-end electronics: V. Re On detector electronics: M. Citterio DAQ: M. Villa Mechanics: F. Bosi Testbeam: S. Bettarini SVT SW: Det Optimization/Fastsim N. Neri Background simulation/Fullsim E. Paoloni (R. Cenci) Layer0 coordination: G. Rizzo Layer1-5 coordination: L. Vitale Construction responsibilities could have a similar scheme, eventually with different names (institutions) attached to each item and finer splitting (like in the SVT – WBS) On detector electronics  Fanouts, HDI, transition cards Mechanics  Layer0, L1-L5 modules, Support structure, cooling. G. Rizzo SVT –Preventivi 2012, June 8 - 2011