Clock Driver PSpice Simulations IUCAA Bhushan Joshi Kalpesh Chillal

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Presentation transcript:

Clock Driver PSpice Simulations IUCAA Bhushan Joshi Kalpesh Chillal Pravin Chordia IUCAA

In-the-loop Compensated Clock Driver Without Transmission line

In-the-loop Compensated Clock Driver Transient Analysis Without Transmission line Transient Analysis

In-the-loop Compensated Clock Driver AC Analysis Without Transmission line AC Analysis

In-the-loop Compensated Clock Driver PSpice Simulations With Transmission line PSpice Simulations

In-the-loop Compensated Clock Driver With Transmission line

In-the-loop Compensated Clock Driver Transient Analysis With Transmission line Transient Analysis

In-the-loop Compensated Clock Driver AC Analysis With Transmission line AC Analysis

Result of Compensated Clock Driver Implemented on test board With Transmission line Transient Analysis (DSO screenshot)

Lead Compensated Clock Driver PSpice Simulations With Transmission line PSpice Simulations Reference(1): Chapter 7,Voltage-Feedback Op Amp Compensation Literature Number SLOA079 Excerpted from Op Amps for Everyone Literature Number: SLOD006A Author : Texas Instruments Page: 7-13 Reference(2): For Calculation of value of capacitor C22 http://www.mathworks.in/products/control/examples.html?file=/products/demos/shipping/control/opampdemo.html

Lead Compensated Clock Driver With Transmission line Since Simulator can not take 0Ω and to keep same schematic 0.1Ω resistor is used

Lead Compensated Clock Driver Transient Analysis With Transmission line Transient Analysis

Lead Compensated Clock Driver AC Analysis With Transmission line AC Analysis

Lead Compensated Clock Driver Implementation on test board With Transmission line Implementation on test board

Clock Driver without any Compensation Load Cap

Result of Clock Driver without any Compensation

Clock Driver with Lead Compensation Changed values Load Cap

Result of Clock Driver with Lead Compensation

Clock Driver with In-the-loop Compensation (Optimized R3,C2 values are selected for 680pF capacitor and transmission line as Load)

OPA4140 Bipolar Bias PSpice Simulations

OPA4140 Bipolar Bias With 50pF capacitor and transmission line as Load BW = 15 MHz PM = 68⁰

OPA4140 Bipolar Bias DC Sweep Analysis

OPA4140 Bipolar Bias With 200pF capacitor and transmission line as Load Instable

OPA4140 Bipolar Bias With 200pF capacitive load and NO transmission line 50Ω Series resistor as suggested in datasheet BW = 8 MHz PM = 45⁰ stable

OPA4140 Bipolar Bias With 200pF capacitor and transmission line as Load 150Ω Series resistor BW = 5 MHz PM = 33⁰ stable Other compensation circuits to be tried