MULTIBOOT AND SPI FLASH MEMORY IFIC (CSIC – Universidad de Valencia) 25 Sept. 2013

MULTIBOOT: Status VHDL reconfiguration Integrate as Wishbone slave Create libraries and driver Slow control using embedded software Write the multiboot images in flash memory using LM32

SPI INTERFACE: LM32 Wishbone slave IP/UDP Packet Buffer Stream Selector (IPMUX) 31 TDCs Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPacket Buffer 64KB RxPort 1 31 PMTs RxPort 2 Rx Stream Select Fifo TDC 30 Rx_mac2buf Rx_buf2data Flags RxPort_m Management & Control S Pause Frame Management & Config. State Machine ADC Fifo Hydrophone TxPacket Buffer 32KB TxPort 1 Management & Control TxPort 2 S Tx_pkt2mac Tx_data2buf Tx Stream Select Multiboot Flags TxPort_m S Management & Control Nano Beacon S WB Crossbar (1x8) M M M S M M M M M M Debug LEDs WB Crossbar (3x2) S M 2nd CPU LM32 M SPI S UART S S S Xilinx Kintex-7 MEM S I2C I2C GPIO S Data UTC time & Clock (PPS, 125 MHz) Control Point to Point interconnection SPI Flash Debug RS232 Temp Compass Tilt Wishbone bus

l SPI FLASH: MEMORY MAP First approach using SPI flash memory available in Kintex 7 Evaluation board CLBv2 flash memory: larger but with similar command set KC705 EV. BOARD CLBv2 Flash Memory N25Q128 (16 Mbytes) N25Q1Gb (128 Mbytes) Sectors 256 (64 Kbytes each) 2048 (64 Kbytes each) Pages 65536 (256 bytes each) 524288 (256 bytes each)

CLBv2 SPI FLASH : MEMORY MAP Free Space Space available in SPI flash memory 48 Mbytes Conf.Parameters Configuration parameters 16 Mbytes Multiboot Image 3 16 Mbytes Diferent Images to reconfigure the system Multiboot Image 2 16 Mbytes Multiboot Image 1 16 Mbytes Stable Image to start up and recovery the system Golden Image 16 Mbytes Base Address

LM32 WB SLAVE: SPI DRIVER SPI Opencores: From the WR repository spi_clock WISHBONE BUS WISHBONE INTERFACE INTERFACE SERIAL CLOCK GENERATOR STARTUP PRIMITIVE SPI DRIVER miso mosi slave enable

LM32 WB SLAVE: SPI PROTOCOL Data from memory (MISO) SPI PROTOCOL: 4 signals Slave Enable (Memory is selected by driving this signal low) SPI clock MOSI (Master Out Slave In) Data from LM32 to flash memory MISO (Master In Slave Out) Data from flash memory to LM32 Slave Memory Enable SPI clock Data to memory (MOSI) Data from memory (MISO)

LM32 WB SLAVE: SLOW CONTROL Library functions implemented: Read Identification Sector Erase Bulk Erase Write status register Read Status register Write enable Write disbale Page program Read SUCCESSFUL TEST!

FLASH PROGRAMMING CHAIN To create the new programming chain (proposed by Vincent) Check the spi driver in the new embedded software (modifiy if needed) Storage Module Flash memory Driver SPI Slow Control Module

FLASH PROGRAMMING TEST Create firmware (HEX or BIN) File MCS file contain information about address and checksum (maybe not needed) Send firmware file to FPGA over serial link (UART Communication) Store it in flash memory using LM32-SPI slow control Reboot FPGA using multiboot slow control